PL500-15 Datasheet, PDF (1/5 Pages) Micrel Semiconductor – Low Phase Noise VCXO (1MHz to 18MHz)

FE AT UR E S
PL500-15/16
Low Phase Noise VCXO (1MHz to 18MHz)
PIN CONFIGURATION
 VCXO with Divider Selection (DIVSEL) input pin
 PL500-15: ÷8, ÷16
 PL500-16: ÷2, ÷4
 VCXO output for the 1MHz to 18MHz range
 16MHz to 36MHz fundamental crystal input.
 Low phase noise (-130 dBc @ 10kHz offset
using a 35.328MHz crystal).
 LVCMOS output with OE tri-state control.
 Integrated high linearity variable capacitors.
 12mA drive capability at TTL output.
 ± 150 ppm pull range, max 5% linearity.
 Low jitter (RMS): 2.5ps period jitter.
 2.5V ~ 3.3V operation.
 Available in 8-Pin SOP, 6-pin SOT23 GREEN/
RoHS compliant packages, or DIE.
DESCRIPTION
The PL500-15/16 is a low cost, high performance
and low phase noise VCXO for the 1MHz to 18MHz
range, providing less than -130dBc at 10kHz offset
when using a 35.328MHz crystal. The very low jitter
(2.5 ps RMS period jitter) makes this chip ideal for
applications requiring voltage controlled frequency
sources. Input crystal can range from 16MHz to
36MHz (fundamental resonant mode).
BLOCK DIAGRAM
XIN 1
VCON 2
DIVSEL^ 3
GND 4
8 XOUT
7 OE^
6 VDD
5 CLK
SOP-8L
VCON 1
GND 2
XIN 3
6 CLK
5 VDD
4 XOUT
SOT23-6L*
^: Denotes internal Pull-up
*: SOT package offers single divider option only
DIVIDER SELECTION LOGIC LEVELS
Part #
DivSel State
Operation
1 (Default)*
÷16
PL500-15
0
÷8
1 (Default)*
÷4
PL500-16
0
÷2
* Setting for SOT23 package
DIVSEL
XIN
XOUT
Xtal
Selectable
Osc
Divider
CLK
VCON
Varicap
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • www.micrel.com Rev 7/01/10 Page 1