PL123-05SC Datasheet, PDF (2/9 Pages) Micrel Semiconductor – Low Skew Zero Delay Buffer

PL123-05/-09
PIN DESCRIPTIONS
Low Skew Zero Delay Buffer
Name
PL123-09
TSSOP-16L SOP-16L
PL123-05
SOP-8L
Type
Description
REF^[1]
1
1
1
I Input reference frequency.
CLKA1^[2]
2
2
3
O Buffered clock output, Bank A
CLKA2^[2]
3
3
2
O Buffered clock output, Bank A
VDD
4,13
4,13
6
P VDD connection
GND
5,12
5,12
4
P GND connection
CLKB1^[2]
6
6
-
O Buffered clock output, Bank B
CLKB2^[2]
7
7
-
O Buffered clock output, Bank B
S2^[3]
8
8
-
I Selector input
S1^[3]
9
9
-
I Selector input
CLKB3^[2]
10
10
-
O Buffered clock output, Bank B
CLKB4^[2]
11
11
-
O Buffered clock output, Bank B
CLKA3^[2]
14
14
5
O Buffered clock output, Bank A
CLKA4^[2]
15
15
CLKOUT^[2]
16
16
7
O Buffered clock output, Bank A
8
O
Buffered clock output. Internal feedback
on this pin.
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2
SELECTOR DEFINITION FOR PL123-09
S2
S1
CLOCK A1–A4 CLOCK B1–B4
(Bank A)
(Bank B)
0
0
Three-state
Three-state
0
1
Driven
Three-state
1
0
Driven
Driven
1
1
Driven
Driven
CLKOUT
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
N
N
Y
N
INPUT / OUTPUT SKEW CONTROL
The PL123-05/-09 will achieve Zero Delay from input to output when all the outputs are loaded equally. Adjust-
ments to the input/output delay can be made by adding additional loading to the CLKOUT pin.
Please contact Micrel for more information.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • www.micrel.com Rev 4/22/13 Page 2