PL123-05SC Datasheet, PDF (1/9 Pages) Micrel Semiconductor – Low Skew Zero Delay Buffer

FEATURES
PL123-05/-09
Low Skew Zero Delay Buffer
DESCRIPTION
 Frequency Range 10MHz to 134 MHz
 Output Options:
o 5 outputs PL123-05
o 9 outputs PL123-09
 Zero input - output delay
 Optional Drive Strength:
Standard (8mA) PL123-05/-09
High (12mA) PL123-05H/-09H
 3.3V, ±10% operation
 Available in Commercial and Industrial temperature
ranges
 Available in 16-Pin SOP or TSSOP (PL123-09),
and 8-Pin SOP (PL123-05) packages
The PL123-05/-09 (-05H/-09H for High Drive) are high
performance, low skew, low jitter zero delay buffers
designed to distribute high speed clocks. They have
one (PL123-05) or two (PL123-09) low-skew output
banks, of 4 outputs each, that are synchronized with
the input. The PL123-09 allows control of the banks of
outputs by using the S1 and S2 inputs as shown in the
Selector Definition table on page 2.
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than 100ps, the device
acts as a zero delay buffer. The input output propaga-
tion delay can be advanced or delayed by adjusting the
load on the CLKOUT pin.
These parts are not intended for 5V input-tolerant ap-
plications.
BLOCK DIAGRAM
REF
PLL
Mux
S1
Selector
Inputs
S2
(PL123-09 Only)
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
REF 1
CLKA2 2
CLKA1 3
GND 4
REF 1
CLKA1 2
CLKA2 3
VDD 4
GND 5
CLKB1 6
CLKB2 7
S2 8
8 CLKOUT
7 CLKA4
6 VDD
5 CLKA3
16 CLKOUT
15 CLKA4
14 CLKA3
13 VDD
12 GND
11 CLKB4
10 CLKB3
9 S1
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • www.micrel.com Rev 4/22/13 Page 1