MIC2589_05 Datasheet, PDF (18/29 Pages) Micrel Semiconductor – Single-Channel, Negative High-Voltage Hot Swap Power Controller/Sequencer

Micrel
t _NLD
=
V_CNLD
×
⎜⎜⎝⎛
C_NLD
I_CNLD
⎟⎟⎠⎞
where V_CNLD = 1.24V (typ); I_CNLD = 25µA (typ); and
C_NLD is an external capacitor connected from Pin 6 to
VEE. Once the voltage on CNLD reaches its no-load
threshold voltage, V_CNLD, the loop times out and the
controller will shut down until it is reset manually
(MIC2589/MIC2595) or until it performs an auto-retry
operation (MIC2589R/MIC2595R). During start-up, the
no-load detection circuit begins to monitor the load
current and the CNLD pin starts ramping along with
the GATE output. In order to keep the output from
shutting down, t_NLD must be long enough to ensure
that the output MOSFET switches on to deliver the
required minimum load-detect current to the output
load before the no-load timer times out.
The Power-Good Output Signals
For
the
MIC2589/MIC2595-1
and
MIC2589R/MIC2595R-1, power-good output signal
PWRGD1 will be high impedance when V_DRAIN drops
below V_PGTH, and will pull-down to the potential at the
DRAIN when V_DRAIN is above V_PGTH. For the
MIC2589/95-2 and the MIC2589R/95R-2, power-good
output signal /PWRGD1 will pull down to the potential
of the DRAIN pin when V_DRAIN drops below V_PGTH and
will be high impedance when V_DRAIN is above V_PGTH.
Hence, the -1 parts have an active-high PWRGDX
signal and the -2 parts have an active-low /PWRGDX
output. PWRGDX (or /PWRGDX) may be used as an
enable signal for one or more following DC/DC
converter modules or for other system uses as
desired. When used as an enable signal, the time
necessary for the PWRGD (or /PWRGD) signal to
pull-up (when in high impedance state) will depend
upon the load (RC) that is present on this output.
Power-good output signals PWRGD2 (/PWRGD2) and
PWRGD3 (/PWRGD3) follow the assertion of
PWRGD1 (/PWRGD1) with a sequencing delay set by
an external capacitor (C_PG) from the controller’s
PGTIMER pin (Pin 2) to VEE. An expression for the
sequencing delay between PWRGD2 and PWRGD1
is given by:
t _{PGDLY2−1}
=
V_THRESH(PG2) × C_PG
I_PGTIMER
where VTHRESH(PG2) (= 0.63V, typically) is the
PWRGD2 threshold voltage for PGTIMER and I_PGTIMER
(= 45µA, typically) is the internal PGTIMER charge
current. Similarly, an expression for the sequencing
delay between PWRGD3 and PWRGD2 is given by:
December 2005
MIC2589/MIC2595
( ) _{tPGDLY3−2 =}
V_THRESH(PG3) − V_THRESH(PG2)
I_PGTIMER
× C_PG
where V_THRESH(PG3) (1.15V, typical) is the PWRGD3
threshold voltage for PGTIMER. Therefore, power-
good output signal PWRGD2 (/PWRGD2) will be
delayed after the assertion of PWRGD1 (/PWRGD1)
by:
t_PGDLY2-1 (ms) ≅ 14 × C_PG(µF)
Power-good output signal PWRGD3 (/PWRGD3)
follows the assertion of PWRGD2 by a delay:
t_PGDLY3-2 (ms) ≅ 11.5 × C_PG(µF)
For example, for a 10µF value for C_PG, power-good
output signal PWRGD2 will be asserted 140ms after
PWRGD1. Power-good signal PWRGD3 will then be
asserted 115ms after PWRGD2 and 255ms after the
assertion of PWRGD1. The relationships between
V_DRAIN, V_PGTH, PWRGD1, PWRGD2, and PWRGD3
are shown in Figure 6.
Undervoltage/Overvoltage Detection (MIC2589 and
MIC2589R)
The MIC2589 and the MIC2589R have “UV” and “OV”
input pins that can be used to detect input supply rail
undervoltage and overvoltage conditions.
Undervoltage lockout prevents the output from
switching on until the supply input is stable and within
tolerance. In a similar fashion, overvoltage shutdown
prevents damage to sensitive circuit components
should the input voltage exceed normal operating
limits. Each of these pins is internally connected to
analog comparators with 20mV of hysteresis. When
the UV pin falls below its V_UVL threshold or the OV pin
is above its V_OVH threshold, the GATE pin is
immediately pulled low. The GATE pin will be held low
until the UV pin is above its V_UVH threshold and the OV
pin is below its V_OVL threshold. The circuit’s UV and
OV threshold voltage levels are programmed using
the resistor divider R1, R2, and R3 as shown in the
“Typical Application” circuit and the equations to set
the trip points are shown below. The circuit’s UV
threshold is set to V_UV = 37V and the OV threshold is
set at V_OV = 72V, values commonly used in Central
Office power distribution applications.
V_UV
=
V_UVL (typ) ×
(R1+ R2 + R3)
(R2 + R3)
V_OV
=
V_OVL
(typ)
×
(R1
+
R2
R3
+
R3)
Given V_UV, V_OV, and any one of the resistor values,
the remaining two resistor values can be determined.
A suggested value for R3 is selected to provide
approximately 100µA (or more) of current through the
voltage divider chain at V_DD = V_UV. This yields the
18
M9999-120505
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