MIC261203ZA_14 Datasheet, PDF (17/29 Pages) Micrel Semiconductor – Synchronous DC-to-DC Buck Regulator

Micrel, Inc.
In each switching cycle of the MIC261203-ZA converter,
the inductor current is sensed by monitoring the low-side
MOSFET in the OFF-time period. If the peak inductor
current is greater than 26A, then the MIC261203-ZA
turns off the high-side MOSFET and a soft-start
sequence is triggered. This mode of operation is called
“hiccup mode” and its purpose is to protect the
downstream load in case of a hard short. The load
current-limit threshold has a foldback characteristic
related to the feedback voltage, as shown in Figure 3.
Current Limit Threshold
vs. Feedback Voltage
30
25
20
15
10
5
0
0.0
0.2
0.4
0.6
0.8
1.0
FEEDBACK VOLTAGE (V)
`
Figure 3. MIC261203-ZA Current-Limit
Foldback Characteristic
Power Good (PG)
The Power Good (PG) pin is an open-drain output that
indicates logic high when the output is nominally 92% of
its steady state voltage. A pull-up resistor of more than
10kΩ should be connected from PG to VDD.
MIC261203-ZA
MOSFET Gate Drive
The Functional Diagram shows a bootstrap circuit,
consisting of D1 (a Schottky diode is recommended) and
C_BST. This circuit supplies energy to the high-side drive
circuit. Capacitor C_BST is charged, while the low-side
MOSFET is on, and the voltage on the SW pin is
approximately 0V. When the high-side MOSFET driver is
turned on, energy from C_BST is used to turn the MOSFET
on. As the high-side MOSFET turns on, the voltage on
the SW pin increases to approximately V_IN. Diode D1 is
reverse biased and C_BST floats high while continuing to
keep the high-side MOSFET on. The bias current of the
high-side driver is less than 10mA so a 0.1μF to 1μF
capacitor is enough to hold the gate voltage with minimal
droop for the power stroke (high-side switching) cycle,
that is, ΔBST = 10mA × 1.67μs/0.1μF = 167mV. When
the low-side MOSFET is turned back on, C_BST is
recharged through D1. A small resistor R_G, in series with
C_BST, can be used to slow down the turn-on time of the
high-side N-channel MOSFET.
The drive voltage is derived from the VDD supply voltage.
The nominal low-side gate drive voltage is VDD and the
nominal high-side gate drive voltage is approximately
VDD – V_DIODE, where V_DIODE is the voltage drop across
D1. An approximate 30ns delay between the high-side
and low-side driver transitions is used to prevent current
from simultaneously flowing unimpeded through both
MOSFETs.
July 22, 2014
17
Revision 1.1