MIC2590B Datasheet, PDF (13/24 Pages) Micrel Semiconductor – Dual-Slot PCI Hot Plug Controller

MIC2590B
A/D Converter
The MIC2590B has a 20-channel, 8-bit A/D converter ca-
pable of monitoring the output voltage and current of each
supply. This information is available via the System Manage-
ment Interface. The information is particularly intended for
use by systems that support the IPMI standard, but may be
used for any desired purpose.
Interrupt Generation
In the MIC2590B, the /INT pin can be asserted (driven low)
whenever a fault condition trips the circuit breaker. The
MIC2590B can thus operate in either polled mode or interrupt
mode. In the polled mode, the Interrupt Mask bit in the
Common Status Register should be set, to prevent the /INT
pin from being asserted. Upon a circuit breaker fault event the
appropriate status bit is also set in the corresponding status
registers. In order to clear the status bit the system must write
a logic 1 back to same bit in the status register. Upon
occurrence of the write the /INT pin will be de-asserted (if
interrupts were enabled), if no other interrupts are pending.
This method of “echo reset” allows data to be retained in the
status registers until such time as the system software is
ready to deal with that data, and then to control the earliest
time at which the next interrupt might occur.
System Management Interface (SMI)
The MIC2590B’s System Management Interface uses the
Read_Byte and Write_Byte subset of the SMBus protocols to
communicate with its host via the System Management
Interface bus. Additionally, the /INT output signals the con-
trolling processor that one or more events need attention, if
an interrupt-driven architecture is used. Note that the
MIC2590B does not participate in the SMBus Alert Response
Address (ARA) portion of the SMBus protocol.
Micrel
The SMBus Read_Byte operation consists of sending the
device’s slave address, followed by the target register’s
internal address, and then clocking out the byte to be read
from the target register. Similarly, the Write_Byte operation
consists of sending the device’s slave address, followed by
the target register’s internal address, and then clocking in the
byte to be written to the target register. The target register
addresses for the MIC2590B are given in Table 4.
MIC2590B SMBus Address Configuration
The MIC2590B responds to its own unique address which is
assigned using A2, A1 and A0. These represent the 3 LSBs
of its 7-bit address, as shown in Table 3. These address bits
are assigned only during power up of the VSTBY supply
input. These three bits allow up to eight MIC2590B devices in
a single system. These pins are either grounded or left
unconnected to specify a logical 0 or 1 respectively. A pin
designated as a logical 1 may also be pulled up to VSTBY.
Inputs
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MIC2590B Slave Address
Binary
Hex
1000 000b
80h
1000 001b
82h
1000 010b
84h
1000 011b
86h
1000 100b
88h
1000 101b
8Ah
1000 100b
8Ch
1000 111b
8Eh
Table 3. MIC2590B SMBus Addressing
AUXEN[x]
ON[x]
AUX OUT[x]
MAIN OUT[x]
FAULT DETECTED
ON AUX OUT[x]
FAULT DETECTED
ON MAIN OUT[x]
/FAULT OUTPUT[x]
/INT OUTPUT
(CLEARED BY SOFTWARE)
Figure 6. Hot Plug Interface Mode Operation
August 2002
13
MIC2590B