MIC23158 Datasheet, PDF (13/20 Pages) Micrel Semiconductor – 3MHz PWM Dual 2A Buck Regulator with HyperLight Load and Power Good

Micrel Inc.
Functional Description
VIN
The input supply (VIN) provides power to the internal
MOSFETs for the switch mode regulator section. The
VIN operating range is 2.7V to 5.5V. An input capacitor
with a minimum voltage rating of 6.3V is recommended.
Due to the high switching speed, a minimum 2.2µF
bypass capacitor placed close to VIN and the power
ground (PGND) pin is required. Refer to the PCB Layout
Recommendations for details.
AVIN
Analog VIN (AVIN) provides power to the internal control
and analog supply circuitry. AVIN and VIN must be tied
together. Careful layout should be considered to ensure
high frequency switching noise caused by VIN is
reduced before reaching AVIN. A 1µF capacitor as close
to AVIN as possible is recommended. Refer to the PCB
Layout Recommendations for details.
EN
A logic high signal on the enable pin activates the output
voltage of the device. A logic low signal on the enable
pin deactivates the output and reduces supply current to
0.1µA. Do not leave the EN pin floating. When disabled,
the MIC23159 switches in a 225Ω load from the SNS pin
to AGND, to discharge the output capacitor.
SW
The switch (SW) connects directly to one end of the
inductor and provides the current path during switching
cycles. The other end of the inductor is connected to the
load, SNS pin, and output capacitor. Due to the high
speed switching on this pin, the switch node should be
routed away from sensitive nodes whenever possible.
SNS
The sense (SNS) pin is connected to the output of the
device to provide feedback to the control circuitry. The
SNS connection should be placed close to the output
capacitor. Refer to the layout recommendations for more
details. The SNS pin also provides the output active
discharge circuit path to pull down the output voltage
when the device is disabled.
AGND
The analog ground (AGND) is the ground path for the
biasing and control circuitry. The current loop for the
signal ground should be separate from the power ground
(PGND) loop. Refer to the PCB Layout
Recommendations for details.
MIC23158/9
PGND
The power ground pin is the ground path for the high
current in PWM mode. The current loop for the power
ground should be as small as possible and separate
from the analog ground (AGND) loop as applicable.
Refer to the layout recommendations for more details.
PG
The power good (PG) pin is an open drain output which
indicates when the output voltage is within regulation.
This is indicated by a logic high signal when the output
voltage is above the PG threshold. Connect a pull up
resistor greater than 5kΩ from PG to V_OUT.
SS
An external soft start circuitry set by a capacitor on the
SS pin reduces inrush current and prevents the output
voltage from overshooting at start up. The SS pin is used
to control the output voltage ramp up time and the
approximate equation for the ramp time in milliseconds
is 296 x 10³ x ln(10) x C_SS. For example, for a C_SS =
470pF, T_RISE ≈ 300µs. Refer to the “V_OUT Rise Time vs.
C_SS” graph in the Typical Characteristics section. The
minimum recommended value for C_SS is 200pF.
FB
The feedback (FB) pin is provided for the adjustable
voltage option. This is the control input for setting the
output voltage. A resistor divider network is connected to
this pin from the output and is compared to the internal
0.62V reference within the regulation loop.
The output voltage can be calculated using Equation 1:
V_OUT
=
V_REF
⋅ 1 + ^R1 
 ^R2 
Eq. 1
Recommended feedback resistor values:
VOUT
1.2V
1.5V
1.8V
2.5V
3.3V
R1
274k
316k
301k
324k
309k
R2
294k
221k
158k
107k
71.5k
November 2012
13
M9999-110812-A