KSZ8895MLUB Datasheet, PDF (13/120 Pages) Micrel Semiconductor – Integrated 5-Port 10/100 Managed Switch

Micrel, Inc.
KSZ8895MLUB
List of Figures
Figure 1. Typical Straight Cable Connection ........................................................................................................................ 26
Figure 2. Typical Crossover Cable Connection .................................................................................................................... 27
Figure 3. Auto-Negotiation .................................................................................................................................................... 28
Figure 4. Destination Address Lookup Flow Chart (Stage 1) ............................................................................................... 34
Figure 5. Destination Address Resolution Flow Chart (Stage 2) .......................................................................................... 35
Figure 6. 802.1p Priority Field Format .................................................................................................................................. 39
Figure 7. Tail Tag Frame Format .......................................................................................................................................... 41
Figure 8. KSZ8895MLUB EEPROM Configuration Timing Diagram .................................................................................... 46
Figure 9. SPI Write Data Cycle ............................................................................................................................................. 47
Figure 10. SPI Read Data Cycle ........................................................................................................................................... 47
Figure 11. SPI Multiple Write ................................................................................................................................................ 48
Figure 12. SPI Multiple Read ................................................................................................................................................ 48
Figure 13. EEPROM Interface Input Receive Timing Diagram........................................................................................... 109
Figure 14. EEPROM Interface Output Transmit Timing Diagram ....................................................................................... 109
Figure 15. SNI Input Timing ................................................................................................................................................ 110
Figure 16. SNI Output Timing ............................................................................................................................................. 110
Figure 17. MAC Mode MII Timing – Data Received from MII ............................................................................................. 111
Figure 18. MAC Mode MII Timing – Data Transmitted from MII ......................................................................................... 111
Figure 19. PHY Mode MII Timing – Data Received from MII.............................................................................................. 112
Figure 20. PHY Mode MII Timing – Data Transmitted from MII.......................................................................................... 112
Figure 21. SPI Input Timing ................................................................................................................................................ 113
Figure 22. SPI Output Timing.............................................................................................................................................. 114
Figure 23. Auto-Negotiation Timing .................................................................................................................................... 115
Figure 24. Reset Timing...................................................................................................................................................... 116
Figure 25. Recommended Reset Circuit ............................................................................................................................. 117
Figure 26. Recommended Circuit for Interfacing with CPU/FPGA Reset........................................................................... 117
April 1, 2014
13
Revision 2.1