KSZ8895MLUB Datasheet, PDF (1/120 Pages) Micrel Semiconductor – Integrated 5-Port 10/100 Managed Switch

General Description
The KSZ8895MLUB is a highly-integrated Layer 2-
managed 5-port switch with an optimized design and
plentiful features, qualified to meet AEC-Q100 standard
for automotive applications. It is designed for cost-
sensitive 10/100Mbps 5-port switch systems with on-chip
termination, lowest power consumption and internal core
power controller. These features will save more system
cost. It has 1.4Gbps high-performance memory
bandwidth, shared memory based switch fabric with full
non-blocking configuration. It also provides an extensive
feature set such as power management, programmable
rate limit and priority ratio, tag/port-based VLAN, packets
filtering, quality-of-service (QoS) four-queue
prioritization, management interface, and MIB counters.
Port 5 is a MAC 5 MII interface with PHY mode as
default at switch side. The SW5-MII interface can be
connected to a processor with a MAC MII interface.
Functional Diagram
KSZ8895MLUB
Integrated 5-Port 10/100 Managed Switch
Revision 2.1
The KSZ8895MLUB consists of 10/100 PHYs with
patented and enhanced mixed-signal technology, media
access control (MAC) units, a high-speed non-blocking
switch fabric, a dedicated address lookup engine, and an
on-chip frame buffer memory. The KSZ8895MLUB
contains five MACs and four integrated PHYs. All PHYs
support 10/100Base-T/TX.
All registers of MACs and PHYs units can be managed
by the SPI interface or the SMI interface. MIIM registers
of the PHYs can be accessed through the MDC/MDIO
interface. EEPROM can set all control registers for the
unmanaged mode.
The KSZ8895MLUB provides multiple CPU control/data
interfaces to effectively address both current and
emerging fast Ethernet applications.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax + 1 [phone] • http://www.micrel.com
April 1, 2014
Revision 2.1