MIC23450_13 Datasheet, PDF (12/22 Pages) Micrel Semiconductor – 3MHz, PWM, 2A Triple Buck Regulator with HyperLight Load® and Power Good

Micrel, Inc.
Functional Description
PVIN
The input supply (PVIN) provides power to the internal
MOSFETs for the switch mode regulator. The VIN
operating range is 2.7V to 5.5V so an input capacitor,
with a minimum voltage rating of 6.3V, is recommended.
Due to the high di/dt switching speeds, a minimum 2.2µF
or 4.7µF recommended bypass capacitor placed close to
PVIN and the power ground (PGND) pin is required.
Refer to the layout recommendations for details.
AVIN
The input supply (AVIN) provides power to the internal
control circuitry. As the high di/dt switching speeds on
PVIN cause small voltage spikes, an RC filter comprising
50Ω and a minimum 100nF decoupling capacitor placed
close to the AVIN and signal ground (AGND) pin is
required.
EN
A logic high signal on the enable pin activates the output
voltage of the device. A logic low signal on the enable
pin deactivates the output and reduces supply current to
0.01µA. MIC23450 features internal soft-start circuitry
that reduces in-rush current and prevents the output
voltage from overshooting at start up. Do not leave the
EN pin floating.
SW
The switch (SW) connects directly to one end of the
inductor and provides the current path during switching
cycles. The other end of the inductor is connected to the
load, SNS pin and output capacitor. Due to the high
speed switching on this pin, the switch node should be
routed away from sensitive nodes.
SNS
The sense (SNS) pin is connected to the output of the
device to provide feedback to the control circuitry. The
SNS connection should be placed close to the output
capacitor. Refer to the layout recommendations for more
details.
AGND
The analog ground (AGND) is the ground path for the
biasing and control circuitry. The current loop for the
signal ground should be separate from the power ground
(PGND) loop. Refer to the layout recommendations for
more details.
MIC23450
PGND
The power ground pin is the ground path for the high
current in PWM mode. The current loop for the power
ground should be as short and wide as possible and
separate from the analog ground (AGND) loop as
applicable. Refer to the layout recommendations for
more details.
PG
The power good (PG) pin is an open drain output which
indicates logic high when the output voltage is typically
above 90% of its steady state voltage. A pull-up resistor
of more than 5kΩ should be connected from PG to V_OUT.
FB
The feedback (FB) pin is the control input for
programming the output voltage. A resistor divider
network is connected to this pin from the output and is
compared to the internal 0.62V reference within the
regulation loop.
The output voltage can be programmed between 1V and
3.3V using Equation 1:
V_OUT
=
V_REF
⋅ 1 + ^R1 
 ^R2 
Eq. 1
Where: R1 is the top, V_OUT connected resistor, R2 is the
bottom, AGND connected resistor.
Table 1 illustrates example feedback resistor values.
VOUT
1.2V
1.5V
1.8V
2.5V
3.3V
R1
274k
316k
301k
324k
309k
R2
294k
221k
158k
107k
71.5k
Table 1. Feedback Resistor Values
November 5, 2013
12
110513-1.1