MIC2130 Datasheet, PDF (12/20 Pages) Micrel Semiconductor – High Voltage Synchronous Buck Control IC with Low EMI Option

Micrel, Inc.
L = Power inductor value
T_DLY = Current limit blanking time ~ 100ns
I_CS(min) = 180µA
Example:
Consider a 12V to 3.3V @ 5A converter with 7.3µH
power inductor and 93% efficiency at a 5A load and an
LSD FET of RDS_ON of 10mΩ (typical values).
D=
V_OUT
V_IN ⋅ Efficiency
I _RIPPLE
= ^{3.3 ⋅ (1 − 0.306)}
150kHz ⋅ 7.3µH
= 2.1A
I _PK
= 5 + ^2.1 = 6.05A
2
I _SET
+ 6.05 − ^{3.3 ⋅ 100ns}
7.3µH
= 6.00A
R_CS
=
6.00 ⋅ 10mΩ
180µA
= 333Ω
(332 std. value)
Using the simple method here would result in a current
limit point lower than desired.
This equation sets the minimum current limit point of the
converter, but maximum will depend upon the actual
inductor value and RDS_ON of the MOSFET under current
limit conditions. This could be in the region of 50%
higher and should be considered to ensure that all the
power components are within their thermal limits unless
thermal protection is implemented separately.
HCL (MIC2131 only)
The high current limit (HCL) is a function of the MIC2131
only. It allows for twice the output load current (for a time
T determined by the HCL cap) before the current limit
comparator trips. During the time T, the current sense
current source (200µA nominal) is increased to 400µA.
T = CHCL * 2/13µ = CHCL * 153.85 *1e3
Where CHCL is the cap at the HCL pin
Frequency Dithering
The MIC2131 has an additional useful feature. The
switching frequency is dithered ±12% in order to spread
the frequency spectrum over a wider range to lower the
EMI noise peaks generated by the switching
components. A pseudo random generator is used to
generate the ±dithering which further reduces the EMI
noise peaks.
MIC2130/1
Power Good Output
The power good output (PG) will go high only when
output is above 90% of the nominal set output voltage.
VDD Regulator
The internal regulator provides a regulated 5V for
supplying the analog circuit power (AV_DD). V_DD also
powers the MOSFET drivers. V_DD is designed to operate
at input voltages down to 8V. The AV_DD supply should be
connected to V_DD through an RC filter to provide
decoupling of the switching noise generated by the
MOSFET drivers taking large current pulses from the
V_DD regulator.
Gate Drivers
The MIC2130/31 is designed to drive both high side and
low side N-Channel MOSFETs to enable high switching
speeds with the lowest possible losses. The high side
MOSFET gate driver is supplied by a bootstrap capacitor
CBST connected at the SW pin and the BST pin. A high
speed diode (a Schottky diode is recommended)
between the V_DD pin and BST pin is required as shown
in Figure 8. This provides the high side MOSFET with a
constant VGS drive voltage equal to V_DD - V_DIODE.
Figure 8.
When HSD goes high, this turns on the high side
MOSFET and the SW node rises sharply. This is
coupled through the bootstrap capacitor CBST and
Diode DBST becomes reverse biased. The MOSFET
Gate is held at V_DD-V_DIODE above the Source for as long
as CBST remains charged. This bias current of the High
side driver is <10mA so a 0.1µF to1 µF is sufficient to
hold the gate voltage with minimal droop for the power
stroke (High side switching) cycle, i.e. ∆BST = 10mA x
6µs / 0.1µF = 567mV. When the low side driver turns on
every switching cycle, any lost charge from CBST is
replaced via DBST as it becomes forward biased.
Therefore minimum BST voltage is V_DD – 0.5V.
The Low side driver is supplied directly from V_DD at
nominal 5V.
April 2008
12
M9999-042108-C