MIC68200 Datasheet, PDF (11/15 Pages) Micrel Semiconductor – 2A Sequencing LDO with Tracking and Ramp Control

Micrel, Inc.
MIC68200
Adjustable Regulator Design
OUT
*CFF
R1
0.1µF
SNS
0.5V
R2
*Required only for large
values of R1 and R2.
COUT
4.7µF
Adjustable Regulator with Resistors
The adjustable MIC68200 output voltage can be
programmed from 0.5V to 5.5V using a resistor divider
from output to the SNS pin. Resistors can be quite
large, up to 1MΩ because of the very high input
impedance and low bias current of the sense
amplifier. Typical sense input currents are less than
30nA which causes less than 0.3% error with R1 and
R2 less than or equal to 100KΩ. For large value
resistors (>50K) R1 should be bypassed by a small
capacitor (C_FF = 0.1µF bypass capacitor) to avoid
instability due to phase lag at the ADJ/SNS input.
The output resistor divider values are calculated by:
VOUT
= 0.5V⎜⎛ ^R1 + 1⎟⎞
⎝ ^R2 ⎠
Power on Reset (POR) and Delay (DLY)
The power-on reset output (POR) is an open-drain
N-Channel device requiring a pull-up resistor to either
the input voltage or output voltage for proper voltage
levels. POR is driven by the internal timer so that the
release of POR at turn-on can be delayed for as much
as 1 second. POR is always pulled low when enable
(EN) is pulled low or the output goes out of regulation
by more than 10% due to loading conditions.
The internal timer is controlled by the DLY pin which
has a bidirectional current source and two limiting
comparators. A capacitor connected from DLY to
GND sets the delay time for two functions. On start
up, DLY sets the time from power good to the release
of the POR. At shut down, the delay sets the time
from disable (EN pin driven low) to actual ramp down
of the output voltage. The current source is +/-1µA,
which charges the capacitor from ~150mV (nominal
disabled DLY voltage) to ~1.25V. At turn on, the DLY
cap begins to charge when the output voltage reaches
90% of the target value. When the capacitor reaches
1.25V, the output of the POR is released to go high.
At turn off, the DLY cap begins to discharge when the
EN is driven low. When the cap reaches ~150mV the
output is ramped down. Both delays are nominally the
same, and are calculated by the same formula:
T_DLY
=
(1.1)_{⎜⎜⎝⎛}
C_DLY
1µ A
⎟⎟⎠⎞
Scale Factor is:
1.1 seconds/microfarad,
1.1 milliseconds/nanofarad, or
1.1 microseconds/picofarad.
T_DLYOFF is the time from lowering of EN to the start of
ramp down on the off cycle. T_POR is the time from
raising of EN to the release (low to high edge) of the
POR. This behavior means that a µP or other
complex logic system is guaranteed that power has
been good for a known time before the POR is
released, and they are further guaranteed that once
POR is pulled low, they have a known time to ‘tidy up’
memory or other registers for a well controlled
shutdown. In Master/Slave configurations the timers
can be used to assure that the Master is always
accurately regulating when the Slave is on.
Ramp Control
The ramp control (RC) has a bidirectional current
source and a sense amplifier, which together are used
to control the voltage at the output. When RC is below
the target voltage (nominal output voltage for fixed
voltage parts, 0.5V for adjustable parts) the RC pin
controls the output voltage. When RC is at or above
the target voltage, the output is controlled by the
internal regulator.
Tracking Applications: Driving RC from a Voltage
Source
Fixed Parts: If RC is driven from another (Master)
regulator the two outputs will track each other until the
Master exceeds the target voltage of the Slave
regulator. Typically the output of the MIC68200 will
track above the RC input by 30mV to 70mV. This
offset is designed to allow Master/Slave tracking of
same-voltage regulators. Without the offset, same-
voltage Master/Slave configurations could suffer poor
regulation.
Adjustable Parts: The RC pin on adjustable versions
operates from 0V to 0.5V. To implement tracking on
an adjustable version, an external resistor divider
must be used. This divider is the nearly same ratio as
the voltage setting divider used to drive the Sense/Adj
pin. It is recommended that the ratio be adjusted to
track ~50mV (2% to 3%) above the target voltage if
the Master and Slave are operating at the same target
voltage.
July 2006
11
M9999-071206
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