KSZ8873MLL_11 Datasheet, PDF (104/108 Pages) Micrel Semiconductor – Integrated 3-Port 10/100 Managed Switch with PHYs

Micrel, Inc.
KSZ8873MLL/FLL/RLL
Reset Timing
The KSZ8873MLL/FLL/RLL reset timing requirement is summarized in the following figure and table.
Figure 32. Reset Timing
Symbols
t_sr
t_cs
t_ch
t_rc
tvr
Parameters
Stable supply voltages to reset High
Configuration setup time
Configuration hold time
Reset to strap-in pin output
3.3V rise time
Table 31. Reset Timing Parameters
Min
Max
Units
10
ms
50
ns
50
ns
50
us
100
us
After the de-assertion of reset, it is recommended to wait a minimum of 100 us before starting programming on the
managed interface (I2C slave, SPI slave, SMI, MIIM).
September 2011
104
M9999-092111-1.5