MIC23254 Datasheet, PDF (10/17 Pages) Micrel Semiconductor – 4MHz Dual 400mA Synchronous Buck Regulator with Low Input Voltage and HyperLight Load™

Micrel, Inc.
MIC23254
Functional Description
VIN
The VIN provides power to the internal MOSFETs for the
switch mode regulator along with the current limit sensing.
The VIN operating range is 2.5V to 5.5V so an input
capacitor with a minimum of 6.3V voltage rating is
recommended. Due to the high switching speed, a
minimum of 2.2µF bypass capacitor placed close to VIN
and the power ground (PGND) pin is required. Based upon
size, performance and cost, a TDK C1608X5R0J475K,
size 0603, 4.7µF ceramic capacitor is highly recommended
for most applications. Refer to the layout
recommendations for details.
AVIN
The analog VIN (AVIN) provides power to the analog
supply circuitry. AVIN and VIN must be tied together.
Careful layout should be considered to ensure high
frequency switching noise caused by VIN is reduced
before reaching AVIN. A 0.01µF bypass capacitor placed
as close to AVIN as possible is recommended. See layout
recommendations for details.
EN1/EN2
The enable pins (EN1 and EN2) control the on and off
states of outputs 1 and 2, respectively. A logic high signal
on the enable pin activates the output voltage of the
device. A logic low signal on each enable pin deactivates
the output. MIC23254 features built-in soft-start circuitry
that reduces in-rush current and prevents the output
voltage from overshooting at start up.
SW1/SW2
The switching pin (SW1 or SW2) connects directly to one
end of the inductor (L1 or L2) and provides the current
path during switching cycles. The other end of the inductor
is connected to the load and SNS pin. Due to the high
speed switching on this pin, the switch node should be
routed away from sensitive nodes.
SNS1/SNS2
The SNS pin (SNS1 or SNS2) is connected to the output
of the device to provide feedback to the control circuitry. A
minimum of 2.2µF bypass capacitor should be connected
in shunt with each output. Based upon size, performance
and cost, a TDK C1608X5R0J475K, size 0603, 4.7µF
ceramic capacitor is highly recommended for most
applications. In order to reduce parasitic inductance, it is
good practice to place the output bypass capacitor as
close to the inductor as possible. The SNS connection
should be placed close to the output bypass capacitor.
Refer to the layout recommendations for more details.
PGND
The power ground (PGND) is the ground path for the high
current in PWM mode. The current loop for the power
ground should be as small as possible and separate from
the Analog ground (AGND) loop. Refer to the layout
recommendations for more details.
AGND
The signal ground (AGND) is the ground path for the
biasing and control circuitry. The current loop for the signal
ground should be separate from the Power Ground
(PGND) loop. Refer to the layout recommendations for
more details.
May 2010
10
M9999-052510