MLX80001 Datasheet, PDF (20/28 Pages) Melexis Microelectronic Systems – 4-channel Master LIN Transceiver

MLX80001
4-channel Master LIN Transceiver
5.2 Duty Cycle Calculation
TxD
V_SUP
100%
BUS
58.1%
28.4%
V_SS 0%
RxD
t_Bit
t_dom(max)
t_dom(min)
t_Bit
t_rec(min)
74.4%
42.2%
t_rec(max)
58.1%
28.4%
Figure 7 - Duty cycle calculation in accordance to LIN 2.x
With the timing parameters shown in Figure 7 two duty cycles , based on t_rec(min)
calculated as follows :
D1 = t_rec(min) / (2 * t_Bit)
D2 = t_rec(max) / (2 * t_Bit)
and t_rec(max)
can be
For proper operation at 20KBit/s ( t_Bit = 50µs) the LIN driver has to fulfill the duty cycles specified in chapter
2.4 for supply voltages of 7 to 18V and the defined standard loads .
Due to this simplified definition there is no need to measure slew rates, slope times, transmitter delays and
dominant voltage levels as specified in the LIN physical layer specification 1.3.
The device within the D1/D2 duty cycle range operates also in applications with reduced bus speed of
10.4KBit/s or below.
In order to minimize EME, the slew rates of the transmitter can be reduced (approximately by 2 times). Such
devices have to fulfill the duty cycle definition D3/D4 in the LIN physical layer specification 2.x. Devices
within this duty cycle range cannot operate in 20KBit/s applications.
MLX80001 – Datasheet
3901080001
Page 20 of 28
March 2007
Rev 001