MLX90323 Datasheet, PDF (17/25 Pages) Melexis Microelectronic Systems – 4 – 20 mA Loop Sensor Interface with Signal Conditioning and EEPROM

MLX90323
4 – 20 mA Loop Sensor Interface
with Signal Conditioning and EEPROM
10 EEPROM and RAM byte definitions
Table 5. EEPROM Byte Definitions
Byte
Designation
Note
0
Turbo mode, temp
Bit 0: must always be set to “1”
selection
Bit 1: (0 = internal temp, 1 = external temp)
Bit 3: (0 = Turbo mode not active, 1 = active)
Bit 2,4,5,6: must always be set to “0”
Bit 7: (0 = EEPROM Checksum test inactive, 1 = active )
1
Cadj
Controls system clock during boot.
2
Coarse Control
Contents described in Table 6.
3
GN1L
The eight LSB's of the Fixed Gain, GN[7:0].
4
OF1L
The eight LSB's of Fixed Offset OF[7:0].
5
GNTC1L
The eight LSB's of the first gain TC GNTC1[7:0].
6
OFTC1L
The eight LSB's of the first offset TC OFTC1[7:0].
7
TR1L
8
GNTC2L
9
OFTC2L
10
TR2L
11
GNTC3L
12
OFTC3L
13
TR3L
14
GNTC4L
15
OFTC4L
16
-
The eight LSB's of the first temperature point, T1[7:0].
The eight LSB's of the second gain TC GNTC2[7:0].
The eight LSB's of the second offset TC OFTC2[7:0].
The eight LSB's of the second temperature point T2[7:0].
The eight LSB's of the third gain TC GNTC3[7:0].
The eight LSB's of the third offset TC OFTC3[7:0]
The eight LSB's of the third temperature point T3[7:0].
The eight LSB's of the fourth gain TC GNTC4[7:0].
The eight LSB's of the fourth offset TC OFTC4.
Reserved
3901090323
Rev 003
Page 17 of 25
Data Sheet
Feb/12