TH8082 Datasheet, PDF (14/26 Pages) List of Unclassifed Manufacturers – Single LIN Bus Transceiver

TH8082
Enhanced SoloLIN Transceiver
The receive threshold values V_{BUS_CNT_max} and V_{BUS_CNT_min} are symmetrical to the centre voltage of 0.5*V_S
with a hysteresis of typ. 0.175*V_S. Including all tolerances the LIN specific receive threshold values of 0.4*V_S
and 0.6*V_S will be secure observed.
The received BUS signal will be output to the RxD pin:
BUS < V_{BUS_CNT} – 0.5 * V_HYS ->
BUS > V_{BUS_CNT} + 0.5 * V_HYS ->
RxD = low (BUS dominant)
RxD = high, floating (BUS recessive)
This pin is a buffered open drain output with a typical load of:
Resistance: 2.7 kOhm
Capacitance: < 25 pF
EN-Pin
The TH8082 is switched into the sleep mode with a falling edge and into normal mode with a rising edge at
the EN pin. The normal mode will be kept as long as EN = high (See Figure 4 – Sleep mode and wake up
procedure for more details).
If the TH8082 is switched to sleep mode also a connected voltage regulator via the INH pin is switched off.
The deactivation of TH8082 with EN = low can be done independent from the state of the bus-transceiver.
The EN input is internal pulled down so that it is secured if this pin is not connected a low level will be
applied.
Datarate
The TH8082 is a constant slew rate transceiver that means the bus driver operates with a fixed slew rate
range of 1.0 V/µs ≤ ∆V/∆T ≤ 3V/µs. This principle secures a very good symmetry of the slope times between
recessive to dominant and dominant to recessive slopes within the LIN bus load range (C_BUS, R_term).
The TH8082 guarantees data rates up to 20kbit within the complete bus load range under worst case
conditions. The constant slew rate principle is very robust against voltage drops and can operate with RC-
oscillator systems with a clock tolerance up to ±2% between 2 nodes.
TH8082 – Datasheet
3901008082
Page 14 of 26
Feb 2007
Rev 007