TH8082 Datasheet, PDF (13/26 Pages) List of Unclassifed Manufacturers – Single LIN Bus Transceiver

TH8082
Enhanced SoloLIN Transceiver
3.4 LIN BUS Transceiver
The transceiver consists a bus-driver (1.2V@40mA) with slew rate control, current limitation and as well in
the receiver a high voltage comparator followed by a debouncing unit.
BUS Input/Output
The recessive BUS level is generated from the integrated 30k pull up resistor in serial with a diode This
diode prevent the reverse current of V_BUS during differential voltage between VS and BUS (V_BUS>V_S).
No additional termination resistor is necessary to use the TH8082 in LIN slave nodes. If this IC is used for
LIN master nodes it is necessary that the BUS pin is terminated via a external 1kΩ resistor in serial with a
diode to VBAT or INH (See chapter 4.4 Short circuit to ground).
TxD Input
During transmission the data at the pin TxD will be transferred to the BUS driver for generating a BUS signal.
To minimize the electromagnetic emission of the bus line, the BUS driver is equipped with an integrated slew
rate control and wave shaping unit.
Transmitting will be interrupted in the following cases:
- Sleep mode
- Thermal Shutdown active
- V_BAT standby
The CMOS compatible input TxD controls directly the BUS level:
TxD = low
->
TxD = high ->
BUS = low (dominant level)
BUS = high (recessive level)
The TxD pin has an internal pull up resistor connected to VCC. This secures that an open TxD pin generates
a recessive BUS level.
RxD Output
The data signals from the BUS pin will be transferred continuously to the pin RxD. Short spikes on the bus
signal are suppressed by the implemented debouncing circuit.
VS
60%
BUS 50%
40%
RxD
VBUS_CNT_max
VhHYS
VBUS_CNT_min
t < t_{rec_deb}
t < t_{rec_deb}
Figure 7 - Receive impulse diagram
TH8082 – Datasheet
3901008082
Page 13 of 26
Feb 2007
Rev 007