MLX90251_12 Datasheet, PDF (14/20 Pages) Melexis Microelectronic Systems – Programmable Linear Hall Effect Sensor

MLX90251
Programmable Linear Hall Effect Sensor
TempCo Range (ppm / °C) Accuracy (ppm / °C)
0 to 500
± 100
500 to 1200
± 150
1200 to 2000
± 200
Table 12: TempCo Accuracy
Note: The budget error of the whole system, the compensation mismatch (system Vs. IC) tolerance should be
taken into consideration during the design. Table 11 is valid for Rough Gain within the specified option code.
See section 10.4 for information on selecting the option code.
10.9 Diagnostic Output Level (FAULTLEV)
The MLX90251 EEPROM memory content is secured through a parity check. This self-diagnostic feature
brings the output to a defined range in case of a parity error. The parameter, FAULTLEV, is used to define
the parity error diagnostic state. With the FAULTLEV set to 0 a parity error event will result in an output
diagnostic voltage low. With the FAULTLEV set to 1 a parity error event will result in an output diagnostic
voltage high. To get rid of the output load influence the output diagnostic voltage level can be fixed to either
Ground (to be used with pull-down load) or V_DD (to be used with pull-up load). Melexis PTC software and
hardware tools have built in functions for calculating and programming the parity.
Note: The MLX90251 EEPROM is also redundant. Each parameter bit is written in three separate cells and a
“majority voting” is applied to determine its status. A parity error is detected only if two out of the three cells
unexpectedly change state. The bits available for the customer ID are not redundant.
10.10 The EEPROM, Parity, and Melexis CRC
The memory cells of the EEPROM are arranged in a table of four columns and one hundred twenty eight
rows. This configuration gives redundancy to the parameters stored in the EEPROM. Each parameter bit is
written in three separate cells in an individual row. A majority voting applied to the three cells determines the
logic status of the bit.
A parameter bit only toggles state in error if two out of three memory cells, within a row, unexpectedly
change. If this happens the feature, PARITY, forces the output voltage to the FAULTLEV diagnostic level.
This ensures the device does not operate with a critical memory fault.
The remaining memory cells are used for data storage. The status of these cells does not effect the device
operation. For example the Customer ID, CUSTID, is stored in this area. Melexis stores the device ID
information, TempCo look-up table and CRC bits in the extra cells. The CRC bits ensure the integrity of the
Melexis data.
Note: To avoid parity and CRC errors, the entire contents of the EEPROM must be read before
programming. Melexis PTC software and hardware tools have built in functions for reading the EEPROM and
handling parity.
10.11 Output Amplifier Configuration (MODE)
The output buffer can be configured to accommodate capacitive loads and improve the saturation voltage
(output swing). The two bit parameter, MODE, sets the current capacity of the output amplifier. Melexis sets
this parameter to 1 at final test. This parameter is not used by the end customer.
10.12 Memory Lock (MEMLOCK)
The Memory Lock feature prevents the device from entering programming mode and from any changes to the
3901090251
Rev 012
Page 14 of 20
Data Sheet
Oct/2012