MG86FE104 Datasheet, PDF (28/134 Pages) Megawin Technology Co., Ltd – Interrupt controller

8.3. Clock Sample Code
(1) Required function: Switch IHRCO from default 24MHz to 22.118MHz
Assembly Code Example:
ORL CKCON0,#(AFS)
; Select IHRCO to output 22.118MHz
C Code Example:
CKCON0 |= AFS;
// Select IHRCO to output 22.1184MHz.
(2). Required Function: Switch SYSCLK to OSCin/1 (default is OSCin/2)
Assembly Code Example:
ANL CKCON0,#(AFS)
; Set SCKS[2:0] = 0 to select OSCin/1
C Code Example:
CKCON0 &= ~(SCKS2 | SCKS1 | SCKS0);
// System clock divider /1
// SCKS[2:0], system clock divider
// 0 | OSCin/1
// 1 | OSCin/2
// 2 | OSCin/4
// 3 | OSCin/8
// 4 | OSCin/16
// 5 | OSCin/32
// 6 | OSCin/64
// 7 | OSCin/128
(3). Required Function: Select XTAL as OSCin source when MCU using IHRCO or ILRCO (default is IHRCO)
Assembly Code Example:
MOV IFADRL,#(CKCON2)
CALL _page_p_sfr_read
; Index Page-P address to CKCON2
; Read CKCON2 data
ORL
CALL
IFD,#( XTALE)
_page_p_sfr_write
; Enable XTALE
;
; Write data to CKCON2, SYSCLK must be less than 25MHz
check_XTOR:
MOV A,AUXR1
JNB ACC.4,check_XTOR
; Check XTAL oscillating ready
; Waiting for XTOR(AUXR1.4) true
ANL
ORL
CALL
IFD,#~(OSCS1 | OSCS0)
IFD,#(OSCS0)
_page_p_sfr_write
; Switch OSCin source to XTAL.
; Write data to CKCON2
ANL IFD,#~(IHRCOE)
CALL _page_p_sfr_write
; Disable IHRCO if MCU is switched from IHRCO
; Write data to CKCON2
C Code Example:
IFADRL = CKCON2;
page_p_sfr_read();
// Index Page-P address to CKCON2
// Read CKCON2 data
IFD |= XTALE;
page_p_sfr_write ();
// Enable XTALE
// Write data to CKCON2, SYSCLK must be less than 25MHz
while(AUXR1 & XTOR == 0x00);
// Check XTAL oscillating ready
// Waiting for XTOR(AUXR1.4) true
IFD &= ~(OSCS1 | OSCS0);
// Switch OSCin source to XTAL.
28
MG86FE/L104 Data Sheet
MEGAWIN