MDT10C61 Datasheet, PDF (7/12 Pages) Micon Design Technology Corporation – 8-bit micro-controller

Note : u unchanged, x unknown, - unimplemented, read as “0”
# value depends on the condition of the following table
MDT10C61
Condition
/MCLR reset (not during SLEEP)
/MCLR reset during SLEEP
WDT reset (not during SLEEP)
WDT reset during SLEEP
Power on reset
Status: bit 4
u
1
0
0
1
Status: bit 3
u
0
1
0
1
Status: bit 1
1
1
1
1
0
Status: bit 0
1
1
1
1
X
8. Instruction Set :
Instruction Code
Mnemonic
Operands
Function
010000 00000000 NOP
No operation
010000 00000001 CLRWT
Clear Watchdog timer
010000 00000010 SLEEP
Sleep mode
010000 00000011 TMODE
Load W to TMODE register
010000 00000100 RET
Return from subroutine
010000 00000rrr CPIO R Control I/O port register
010001 1rrrrrrr STWR R Store W to register
011000 trrrrrrr
LDR R, t Load register
111010 iiiiiiii
LDWI I
Load immediate to W
010111 trrrrrrr
SWAPR R, t Swap halves register
011001 trrrrrrr
INCR R, t Increment register
011010 trrrrrrr
INCRSZ R, t Increment register, skip if zero
011011 trrrrrrr
ADDWR R, t Add W and register
011100 trrrrrrr
SUBWR R, t Subtract W from register
011101 trrrrrrr
DECR R, t Decrement register
011110 trrrrrrr
DECRSZ R, t Decrement register, skip if zero
010010 trrrrrrr
ANDWR R, t AND W and register
110100 iiiiiiii
ANDWI i AND W and immediate
010011 trrrrrrr
IORWR R, t Inclu. OR W and register
110101 iiiiiiii
IORWI i Inclu. OR W and immediate
010100 trrrrrrr
XORWR R, t Exclu. OR W and register
110110 iiiiiiii
XORWI i Exclu. OR W and immediate
011111 trrrrrrr
COMR R, t Complement register
Operating
None
0 WT
0 WT, stop OSC
W TMODE
Stack PC
W CPIO r
WR
Rt
IW
[R(0~3)↔R(4~7)] t
R+1 t
R+1 t
W+R t
R W t or (R+/W+1 t)
R 1t
R 1t
R Wt
i WW
R Wt
i WW
R Wt
i WW
/R t
Status
TF, PF
TF, PF
None
None
None
None
Z
None
None
Z
None
C, HC, Z
C, HC, Z
Z
None
Z
Z
Z
Z
Z
Z
Z
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 7
2005/6 Ver. 1.7