MDT10P223 Datasheet, PDF (11/21 Pages) Micon Design Technology Corporation – 8-bit micro-controller

MDT10P223
Register Address Power-On Reset /MCLR Reset WDT Reset
STATUS
03h
0001 1xxx
000# #uuu
000# #uuu
MSR
04h
100x xxxx
100u uuuu
1uuu uuuu
PORT A
05h
xxxx xxxx
uuuuuuuu
uuuu uuuu
PORT B
06h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CMR
07h
0000 0000
uuuu uuuu
uuuu uuuu
Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0”
#＝value depends on the condition of the following table
Condition
/MCLR reset (not during SLEEP)
/MCLR reset during SLEEP
WDT reset (not during SLEEP)
WDT reset during SLEEP
Status: bit 4
U
1
0
0
Status: bit 3
u
0
1
0
10. Instruction Set
Instruction Code
Mnemonic
Operands
Function
Operating
Status
010000 00000000 NOP
No operation
None
010000 00000001 CLRWT
Clear Watchdog timer
0→WT
TF, PF
010000 00000010 SLEEP
Sleep mode
0→WT, stop OSC TF, PF
010000 00000011 TMODE
Load W to TMODE register W→TMODE
None
010000 00000100 RET
Return
Stack→PC
None
010000 00000rrr CPIO R Control I/O port register W→CPIO r
None
010001 1rrrrrrr STWR R Store W to register
W→R
None
011000 trrrrrrr LDR R, t Load register
R→t
Z
111010 iiiiiiii
LDWI I
Load immediate to W
I→W
None
010111 trrrrrrr SWAPR R, t Swap halves register
[R(0~3)↔R(4~7)] None
→t
011001 trrrrrrr INCR R, t Increment register
R + 1→t
Z
011010 trrrrrrr
INCRSZ R, t Increment register, skip if R + 1→t
zero
None
011011 trrrrrrr ADDWR R, t Add W and register
W + R→t
C, HC, Z
011100 trrrrrrr
011101 trrrrrrr
SUBWR R, t Subtract W from register
DECR R, t Decrement register
R ﹣W→t
(R+/W+1→t)
R ﹣1→t
C, HC, Z
Z
011110 trrrrrrr
DECRSZ R, t Decrement register, skip if R ﹣1→t
zero
None
010010 trrrrrrr ANDWR R, t AND W and register
R ∩ W→t
Z
This specification are subject to be changed without notice. Any latest information
Please visit http;//www.mdtic.com.tw
P.11
2010/06 Ver. 1.0