MX10E80501 Datasheet, PDF (53/88 Pages) Macronix International – On-chip Flash program memory with in-system programming

PRELIMINARY
MX10E8050I /
MX10E8050IA
CR0, CR1, and CR2 do not affect SIO1 in the slave mode. ENS1 must be set to logic 1 to enable SIO1. The AA bit
must be set to enable SIO1 to acknowledge its own slave address or the general call address. STA, STO, and SI must
be reset.
When S1ADR and S1CON have been initialized, SIO1 waits until it is addressed by its own slave address followed by
the data direction bit which must be “0” (W) for SIO1 to operate in the slave receiver mode. After its own slave
address and the W bit have been received, the serial interrupt flag (I) is set and a valid status code can be read from
S1STA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for
each of these status codes is detailed in Table 23. The slave receiver mode may also be entered if arbitration is lost
while SIO1 is in the master mode (see status 68H and 78H).
If the AA bit is reset during a transfer, SIO1 will return a not acknowledge (logic 1) to SDA after the next received data
byte. While AA is reset, SIO1 does not respond to its own slave address or a general call address. However, the I²C
bus is still monitored and address recognition may be resumed at any time by setting AA. This means that the AA bit
may be used to temporarily isolate SIO1 from the I²C bus.
P/N:PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.6, MAR. 28, 2005
53