MX25L12875F Datasheet, PDF (47/102 Pages) Macronix International – 3V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY

MX25L12875F
Figure 35. 4 x I/O Read enhance performance Mode Sequence (SPI Mode)
CS#
SCLK
SIO0
Mode 3 _{0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22}
Mode 0
Command
EBh
6 ADD Cycles
(Note 2)
Performance
enhance
indicator (Note 1)
Configurable
Dummy Cycle (Note 2)
A20 A16 A12 A8 A4 A P4 P0
Data
Out 1
Data
Out 2
D4 D0 D4 D0
n
Data
Out n
D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1
D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2
D6 D2
SIO3
CS#
SCLK
SIO0
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3
D7 D3
n+1 ...........
n+7 ......n+9 ........... n+13 ...........
Mode 3
6 ADD Cycles
(Note 2)
Performance
enhance
indicator (Note 1)
Configurable
Dummy Cycle (Note 2)
Data
Out 1
Data
Out 2
A20 A16 A12 A8 A4 A P4 P0
D4 D0 D4 D0
Data
Out n
Mode 0
D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1
D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2
D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3
D7 D3
Notes:
1. If not using performance enhance recommend to keep 1 or 0 in performance enhance indicator.
2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.
P/N: PM1855
REV. 1.1, OCT. 31, 2013
47