MX25L1675E Datasheet, PDF (32/65 Pages) Macronix International – 16M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY

MX25L1675E
9-14. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see "Table 4. Memory Organization" ) is a valid address
for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address
byte has been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI
→CS# goes high.
The SIO[3:1] are don't care when during this mode.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Pro-
gress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE
timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page
is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
Figure 16. Sector Erase (SE) Sequence (Command 20)
CS#
SCLK
0123456789
29 30 31
Command
24 Bit Address
SI
20h
23 22
210
MSB
P/N: PM1850
REV. 1.2, NOV. 11, 2013
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