MX25L1675E Datasheet, PDF (28/65 Pages) Macronix International – 16M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY

MX25L1675E
9-11. 4 x I/O Read Mode (4READ)
The 4READ instruction enables quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,
and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address
counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following
address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address inter-
leave on SIO3, SIO2, SIO1 & SIO0→ 2+4 dummy cycles→ data out interleave on SIO3, SIO2, SIO1 & SIO0→ to
end 4READ operation can use CS# to high at any time during data out.
Figure 13. 4 x I/O Read Mode Sequence (Command EB)
CS#
SCLK
SI/SIO0
SO/SIO1
WP#/SIO2
NC/SIO3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
8 Bit Instruction
EB(hex)
High Impedance
High Impedance
High Impedance
6 Address cycles
address
bit20, bit16..bit0
Performance
enhance
indicator (Note)
P4 P0
4 dummy
cycles
address
bit21, bit17..bit1
P5 P1
address
bit22, bit18..bit2
P6 P2
address
bit23, bit19..bit3
P7 P3
Data Output
data
bit4, bit0, bit4....
data
bit5 bit1, bit5....
data
bit6 bit2, bit6....
data
bit7 bit3, bit7....
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
P/N: PM1850
REV. 1.2, NOV. 11, 2013
28