MX25L12855EMI-10G Datasheet, PDF(32/81 Page) Macronix International – HIGH PERFORMANCE SERIAL FLASH SPECIFICATION

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MX25L12855EMI-10G Datasheet, PDF (32/81 Pages) Macronix International – HIGH PERFORMANCE SERIAL FLASH SPECIFICATION

◁

MX25L6455E

MX25L12855E

(29) Write Protection Selection (WPSEL)

There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WPSEL=0,

flash is under BP protection mode . If WPSEL=1, flash is under individual block protection mode. The default value

of WPSEL is â0â. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an OTP bit. Once

WPSEL is set to 1, there is no chance to recovery WPSEL back to â0â. If the flash is put on BP mode, the indi-

vidual block protection mode is disabled. Contrarily, if flash is on the individual block protection mode, the BP mode

is disabled.

Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1, all

the blocks or sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK

and GBULK instruction. Program or erase functions can only be operated after the Unlock instruction is conducted.

BP protection mode, WPSEL=0:

ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by âSRWD=1 and WP#=0â, where SRWD is bit 7

of status register that can be set by WRSR command.

Individual block protection mode, WPSEL=1:

Blocks are individually protected by their own SRAM lock bits which are set to â1â after power up. SBULK and SBLK

command can set SRAM lock bit to â0â and â1â. When the system accepts and executes WPSEL instruction, the bit

7 in security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct

block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block meth-

ods. Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0.

Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.

The sequence of issuing WPSEL instruction is: CS# goes low â sending WPSEL instruction to enter the individual

block protect mode â CS# goes high.

WPSEL instruction function flow is as follows:

BP and SRWD if WPSEL=0

WP# pin

64KB

BP3 BP2 BP1 BP0

SRWD

64KB

(1) BP3~BP0 is used to define the protection group region.

(The protected area size see Table2)

(2) âSRWD=1 and WP#=0â is used to protect BP3~BP0. In this

case, SRWD and BP3~BP0 of status register bits can not

be changed by WRSR

64KB

P/N: PM1467

REV. 1.4, FEB. 10, 2012

▷