MX25L512EMI-10G Datasheet, PDF (25/49 Pages) Macronix International – 512K-BIT [x 1/x 2] CMOS SERIAL FLASH

MX25L512E
POWER-ON STATE
The device is at the states as below when power-up:
- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level (Please refer to the figure of "power-up timing"):
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal Power-On Reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the time delay: tVSL after VCC
reached VCC minimum level. Please refer to the figure of "power-up timing".
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend-
ed.(generally around 0.1uF)
P/N: PM1669
REV. 1.1, FEB. 10, 2012
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