MX25L512EMI-10G Datasheet, PDF (17/49 Pages) Macronix International – 512K-BIT [x 1/x 2] CMOS SERIAL FLASH

MX25L512E
executed. If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request
page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at
the request address of the page without effect on other address of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high. (see Figure 19)
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
(13) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-
ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac-
tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep
power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (see Fig-
ure 22)
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Power-
down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(14) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID
Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng,
please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed,
only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/
write cycle in progress.
The sequence is shown as Figure 24 and Figure 25.
P/N: PM1669
REV. 1.1, FEB. 10, 2012
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