MX25U25635F Datasheet, PDF (23/96 Pages) Macronix International – 1.8V 256M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY

MX25U25635F
9-2. Write Disable (WRDI)
The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in
SPI mode.
The WEL bit is reset by following situations:
- Power-up
- Reset# pin driven low
- WRDI command completion
- WRSR command completion
- PP/PP4B command completion
- 4PP/4PP4B command completion
- SE/SE4B command completion
- BE32K/BE32K4B command completion
- BE/BE4B command completion
- CE command completion
- PGM/ERS Suspend command completion
- Softreset command completion
- WRSCUR command completion
- WREAR command completion
- WRFBR command completion
- ESFBR command completion
Figure 9. Write Disable (WRDI) Sequence (SPI Mode)
CS#
Mode 3
SCLK
Mode 0
SI
SO
01234567
Command
04h
High-Z
Figure 10. Write Disable (WRDI) Sequence (QPI Mode)
CS#
SCLK
Mode 3
Mode 0
SIO[3:0]
01
Command
04h
P/N: PM1712
REV. 1.2, NOV. 28, 2013
23