MX29NS640E Datasheet, PDF (18/70 Pages) Macronix International – 128/64/32M-BIT [8/4/2M x16-bit] CMOS 1.8 Volt-only,

MULTIPLEXED, Burst Mode, Flash Memory
NOTES:
1. WP# protects the top two sectors.
2. ACC low protects all sectors.
3. Q0~Q15 are input (DIN) or output (DOUT) pins according to the requests of command
sequence, sector protection, or data polling algorithm.
4. In Word Mode, the addresses are AM to A0, AM: MSB of address.
5-1. Non-Burst (Asynchronous) Read Operation
Upon device's power-up, non-burst mode read is as the default state. To perform a read operation,
the system addresses the desired memory array or status register location by providing its address
on the address pins and simultaneously enabling the chip by driving AVD# & CE# LOW, and WE#
HIGH. The CLK keeps low during asynchronous read operation. The address is latched on the
rising edge of AVD#; OE# will be driven low afterwards. A/Q15-A/Q0 output the data after previous
operations is complete.
5-2. Burst (Synchronous) Read Operation
The device supports the following burst read modes:
- Continuous burst read
- Linear burst reads (8/16 words) with/without wrap around
5-2-1. Continuous Burst Read
Burst read mode is enabled when first CLK rising edge meets AVD# low period. The AVD# keeps
low for no more than one clock cycle.
The number of dummy cycles should be set (for tIACC for each burst session) before the clock
signal is being activated. Before the burst read mode is activated, the number of dummy cycle will
be determined by the setting configuration register command.
The process of the continuous burst read operation is as follows:
First CLK cycle's rising edge --> Initial word output tIACC --> Wait for dummy cycle --> Rising
rising edge of each consecutive clock, following words output (tBACC) (Automatically increase the
internal address counter)
1. For address boundary every 8 words, the first boundary starts with 000007h, next with 00000Fh
by adding 8 words address; and etc.
2. For address boundary every 128 words, the first boundary starts with 00007Fh, next with
0000FFh by adding 128 words address; and etc.
3. Additional dummy cycles are needed if the start address for the output cannot be divided by 4.
RDY status indicates the condition of the device by de-asserting.
NOTE: There is a permanent internal address boundary in the device that occurs
8 or 128 words. Boundary crossing latency is needed when the device
operates with dummy cycles set from 5 to 10.
P/N: PM1585
REV. 1.1, APR. 26, 2011
18