69F1608_08 Datasheet, PDF (26/33 Pages) Maxwell Technologies – 128 Megabit (16M x 8-Bit) Flash Memory Module

128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
BLOCK ERASE
The Erase operation can erase on a block (8K Byte) basis. Block address loading is accomplished in two
cycles initiated by an Erase Setup command (60h). Only address A13 to A21 is valid while A9 to A12 is
ignored. The addresses of the block to be erased to FFh. The Erase Confirm command (D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by
execution ensures that memory contents are not accidentally erased due to external noise conditions. At the
rising edge of WE after the erase confirm command input, the internal write controller handles erase and
erase-verify. When the erase operation is completed, the Write Status Bit (I/O0) may be checked. Figure 27
details the sequence.
FIGURE 27. BLOCK ERASE OPERATION
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is
complete, and whether the program or erase operation completed successfully. After writing 70h command
to the command register, a read cycle outputs the contents of the Status Register to the I/O pins on the fall-
ing edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of
each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not
need to be toggled for updated status. Refer to table 14 for specific Status Register definitions. The com-
mand register remains in Status Read mode until further commands are issued to it. Therefore, if the status
register is read during a random read cycle, a read command (00h or 50h) should be given before sequential
page read cycle.
03.07.08 REV 3
All data sheets are subject to change without notice 26
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