MAX127 Datasheet, PDF (9/16 Pages) Maxim Integrated Products – Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface

Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
SDA
A2
A1
A0
SCL
SHDN
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
REF
REFADJ
ANALOG
INPUT
MUX
AND SIGNAL
CONDITIONING
2.5V
10k
REFERENCE
SERIAL INTERFACE LOGIC
INT
CLOCK
T/H
A_V =
1.638
OUT
IN
REF
CLOCK
12-BIT SAR ADC
MAX127
MAX128
V_DD
AGND
DGND
Figure 1. Block Diagram
Detailed Description
Converter Operation
The MAX127/MAX128 multirange, fault-tolerant ADCs
use successive approximation and internal track/hold
(T/H) circuitry to convert an analog signal to a 12-bit
digital output. Figure 1 shows the block diagram for
these devices.
Analog-Input Track/Hold
The T/H circuitry enters its tracking/acquisition mode on
the falling edge of the sixth clock in the 8-bit input con-
trol word and enters its hold/conversion mode when the
master issues a STOP condition. For timing information,
see the Start a Conversion section.
Input Range and Protection
The MAX127/MAX128 have software-selectable input
ranges. Each analog input channel can be indepen-
dently programmed to one of four ranges by setting the
appropriate control bits (RNG, BIP) in the control byte
(Table 1). The MAX127 has selectable input ranges
extending to ±10V (±V_REF x 2.441), while the MAX128
has selectable input ranges extending to ±V_REF. Note
that when an external reference is applied at REFADJ,
the voltage at REF is given by V_REF = 1.638 x V_REFADJ
(2.4 < V_REF < 4.18). Figure 2 shows the equivalent
input circuit.
A resistor network on each analog input provides a
±16.5V fault protection for all channels. This circuit lim-
its the current going into or out of the pin to less than
1.2mA, whether or not the channel is on. This provides
an added layer of protection when momentary over-
voltages occur at the selected input channel, and when
a negative signal is applied at the input even though
R1
CH_
BIPOLAR
S1
VOLTAGE
REFERENCE
5.12k
S2
R2
UNIPOLAR
OFF
C_HOLD
ON
HOLD
S3
TRACK
TRACK
S4
T/H
OUT
HOLD
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
R1 = 12.5kΩ (MAX127) OR 5.12kΩ (MAX128)
R2 = 8.67kΩ (MAX127) OR ∞ (MAX128)
Figure 2. Equivalent Input Circuit
the device may be configured for unipolar mode.
Overvoltage protection is active even if the device is in
power-down mode or V_DD = 0.
Digital Interface
The MAX127/MAX128 feature a 2-wire serial interface
consisting of the SDA and SCL pins. SDA is the data
I/O and SCL is the serial clock input, controlled by the
master device. A2–A0 are used to program the
MAX127/MAX128 to different slave addresses. (The
MAX127/MAX128 only work as slaves.) The two bus
lines (SDA and SCL) must be high when the bus is not
in use. External pull-up resistors (1kΩor greater) are
required on SDA and SCL to maintain I²C compatibility.
Table 1 shows the input control-byte format.
_______________________________________________________________________________________ 9