MAX127 Datasheet, PDF (11/16 Pages) Maxim Integrated Products – Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface

Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
Slave Address
The MAX127/MAX128 have a 7-bit-long slave address.
The first four bits (MSBs) of the slave address have
been factory programmed and are always 0101. The
logic state of the address input pins (A2–A0) determine
the three LSBs of the device address (Figure 3). A max-
imum of eight MAX127/MAX128 devices can therefore
be connected on the same bus at one time.
A2–A0 may be connected to V_DD or DGND, or they
may be actively driven by TTL or CMOS logic levels.
The eighth bit of the address byte determines whether
the master is writing to or reading from the MAX127/
MAX128 (R/W = 0 selects a write condition. R/W = 1
selects a read condition).
Conversion Control
The master signals the beginning of a transmission with
a START condition (S), which is a high-to-low transition
on SDA while SCL is high. When the master has fin-
ished communicating with the slave, the master issues
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high (Figure 4). The bus is then
free for another transmission. Figure 5 shows the timing
diagram for signals on the 2-wire interface. The
address-byte, control-byte, and data-byte are transmit-
ted between the START and STOP conditions. The SDA
state is allowed to change only while SCL is low, except
for the START and STOP conditions. Data is transmitted
in 8-bit words. Nine clock cycles are required to trans-
fer the data in or out of the MAX127/MAX128. (Figures
9 and 10).
SLAVE ADDRESS
0
SDA
SCL
10
1 A2 A1 A0 R/W ACK
LSB
SLAVE ADDRESS BITS A2, A1, AND A0 CORRESPOND TO THE LOGIC STATE
OF THE ADDRESS INPUT PINS A2, A1, AND A0.
Figure 3. Address Byte
SDA
SCL
START CONDITION
STOP CONDITION
Figure 4. START and STOP Conditions
SDA
t_SU, _DAT
t_LOW
t_HD, _DAT
SCL
t_HD, _STA
START CONDITION
t_HIGH
t_R
t_F
t_SU, _STA
t_HD, _STA
REPEATED START CONDITION
t_BUF
t_SU, _STO
STOP CONDITION START CONDITION
Figure 5. 2-Wire Serial-Interface Timing Diagram
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