MAX1224 Datasheet, PDF (9/18 Pages) Maxim Integrated Products – 1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs

1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
REF
AIN+
T/H
AIN-
V_DD
V_L
12-BIT
SAR
ADC
OUTPUT
BUFFER
DOUT
MAX1224
MAX1225
CONTROL
LOGIC AND
TIMING
RGND
GND
CNVST
SCLK
Figure 3. Functional Diagram
Detailed Description
The MAX1224/MAX1225 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. The
serial interface requires only three digital lines (SCLK,
CNVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1224/MAX1225.
True-Differential Analog Input T/H
The equivalent circuit of Figure 4 shows the input archi-
tecture of the MAX1224/MAX1225, which is composed
of a T/H, a comparator, and a switched-capacitor digi-
tal-to-analog converter (DAC). The T/H enters its track-
ing mode on the 14th SCLK rising edge of the previous
conversion. Upon power-up, the T/H enters its tracking
mode immediately. The positive input capacitor is con-
nected to AIN+. The negative input capacitor is con-
nected to AIN-. The T/H enters its hold mode on the
falling edge of CNVST and the difference between the
sampled positive and negative input voltages is con-
verted. The time required for the T/H to acquire an input
signal is determined by how quickly its input capaci-
tance is charged. If the input signal’s source imped-
ance is high, the acquisition time lengthens. The
acquisition time, t_ACQ, is the minimum time needed for
C_{IN+ RIN+}
AIN+
CAPACITIVE
DAC
V_AZ
COMP
CONTROL
LOGIC
AIN-
C_IN- ^RIN- _{ACQUISITION MODE}
C_{IN+ RIN+}
AIN+
CAPACITIVE
DAC
V_AZ
COMP
CONTROL
LOGIC
AIN-
C_IN- ^RIN-
HOLD/CONVERSION MODE
Figure 4. Equivalent Input Circuit
the signal to be acquired. It is calculated by the follow-
ing equation:
t_ACQ ≥ 9 x (RS + R_IN) x 16pF
where R_IN = 200Ω, and RS is the source impedance of
the input signal.
Note: t_ACQ is never less than 125ns, and any source
impedance below 12Ω does not significantly affect the
ADC’s AC performance.
Input Bandwidth
The ADC’s input-tracking circuitry has a 15MHz small-
signal bandwidth, making it possible to digitize high-
speed transient events and measure periodic
signals with bandwidths exceeding the ADC’s sam-
pling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended.
Analog Input Protection
Internal protection diodes that clamp the analog input
to V_DD and GND allow the analog input pins to swing
from GND - 0.3V to V_DD + 0.3V without damage. Both
inputs must not exceed V_DD or be lower than GND for
accurate conversions.
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