MAX1224 Datasheet, PDF (12/18 Pages) Maxim Integrated Products – 1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs

1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
OUTPUT CODE
111...111
111...110
111...101
FULL-SCALE
TRANSITION
000...011
000...010
000...001
000...000
012 3
FS = V_REF
ZS = 0
1 LSB = ^VREF
4096
DIFFERENTIAL INPUT
VOLTAGE (LSB)
FS
FS - 3/2 LSB
Figure 8. Unipolar Transfer Function (MAX1224 Only)
OUTPUT CODE
011...111
011...110
000...010
000...001
000...000
111...111
111...110
111...101
FS = ^VREF
2
ZS = 0
- FS = ^-VREF
2
1 LSB = ^VREF
4096
FULL-SCALE
TRANSITION
100...001
100...000
-FS
0
FS
DIFFERENTIAL INPUT
FS - 3/2 LSB
VOLTAGE (LSB)
Figure 9. Bipolar Transfer Function (MAX1225 Only)
Connection to
Standard Interfaces
The MAX1224/MAX1225 serial interface is fully compati-
ble with SPI/QSPI and MICROWIRE (see Figure 11). If a
serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 28.8MHz.
SPI and MICROWIRE
When using SPI or MICROWIRE, the MAX1224/MAX1225
are compatible with all four modes programmed with the
CPHA and CPOL bits in the SPI or MICROWIRE control
register. Conversion begins with a CNVST falling edge.
DOUT goes low, indicating a conversion is in progress.
Two consecutive 1-byte reads are required to get the full
12 bits from the ADC. DOUT transitions on SCLK rising
edges. DOUT is guaranteed to be valid t_DOUT later and
remains valid until t_DHOLD after the following SCLK rising
edge. When using CPOL = 0 and CPHA = 0, or CPOL =
1 and CPHA = 1, the data is clocked into the µP on the
following rising edge. When using CPOL = 0 and CPHA
= 1, or CPOL = 1 and CPHA = 0, the data is clocked
into the µP on the next falling edge. See Figure 11 for
connections and Figures 12 and 13 for timing. See the
Timing Characteristics section to determine the best
mode to use.
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1224/MAX1225 require 16 clock cycles
from the µP to clock out the 12 bits of data. Figure 14
shows a transfer using CPOL = 1 and CPHA = 1. The
conversion result contains three zeros, followed by the
12 data bits, and a trailing zero with the data in MSB-
first format.
DSP Interface to the TMS320C54_
The MAX1224/MAX1225 can be directly connected
to the TMS320C54_ family of DSPs from Texas
Instruments, Inc. Set the DSP to generate its own
clocks or use external clock signals. Use either the
standard or buffered serial port. Figure 15 shows the
simplest interface between the MAX1224/MAX1225 and
the TMS320C54_, where the transmit serial clock
(CLKX) drives the receive serial clock (CLKR) and
SCLK, and the transmit frame sync (FSX) drives the
receive frame sync (FSR) and CNVST.
For continuous conversion, set the serial port to trans-
mit a clock, and pulse the frame sync signal for a clock
period before data transmission. The serial-port config-
uration (SPC) register should be set up with internal
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