MAX1171 Datasheet, PDF (9/12 Pages) Maxim Integrated Products – 12-Bit, 20Msps, TTL-Output ADC

12-Bit, 20Msps, TTL-Output ADC
AGND and DGND are the two grounds available on the
MAX1171. These two internal grounds are isolated on
the device. The use of ground planes is recommended
to achieve optimum device performance. DGND is
needed for the DV_CC return path (40mA typical) and for
the return path for all digital output logic interfaces.
AGND and DGND should be separated from each
other and connected together only at the device
through a ferrite bead.
A Schottky or hot carrier diode connected between
AGND and V_EE is required. The use of separate power
supplies between V_CC and DV_CC is not recommended
due to potential power-supply sequencing latchup con-
ditions. Use of the recommended interface circuit shown
in Figure 2 will provide optimum device performance for
the MAX1171.
Voltage Reference
The MAX1171 requires the use of two voltage refer-
ences: V_FT and V_FB. V_FT is the force for the top of the
voltage reference ladder (+2.5V typical), V_FB (-2.5V
typical) is the force for the bottom of the voltage refer-
ence ladder. Both voltages are applied across an inter-
nal reference ladder resistance of 800Ω. The +2.5V
voltage source for reference V_FT must be current limit-
ed to 20mA maximum if a different driving circuit is
used in place of the recommended reference circuit
shown in Figures 2 and 3.
In addition, there are five reference ladder taps (V_ST,
VR_T1, VR_T2, VR_T3, and V_SB). V_ST is the sense for the
top of the reference ladder (+2.0V), VR_T2 is the mid-
point of the ladder (0.0V typical), and V_SB is the sense
for the bottom of the reference ladder (-2.0V). VR_T1 and
VR_T3 are quarter-point ladder taps (+1.0V and -1.0V
typical, respectively). The voltages seen at V_ST and
V_SB are the true full-scale input voltages of the device
when V_FT and V_FB are driven to the recommended volt-
ages (+2.5V and -2.5V typical, respectively). V_ST and
V_SB can be used to monitor the actual full-scale input
voltage of the device. VR_T1, VR_T2, and VR_T3 should not
be driven to the expected ideal values, as is commonly
done with standard flash converters. A decoupling
capacitor of 0.01µF connected to AGND from each tap
is recommended to minimize high-frequency noise
injection.
The analog input range will scale proportionally with
respect to the reference voltage if a different input
V_CC
V_IN
V_FT
V_EE
Figure 3. Analog Equivalent Input Circuit
range is required. The maximum scaling factor for
device operation is ±20% of the recommended refer-
ence voltages of V_FT and V_FB. However, because the
MAX1171 is laser trimmed to optimize performance
with ±2.5V references, its accuracy will degrade if
operated beyond a ±2% range.
An example of a recommended reference driver circuit
is shown in Figure 2. IC1 is REF-03, the +2.5V refer-
ence with a tolerance of 0.6% or ±0.015V. The 10kΩ
potentiometer supports an adjustable range of 150mV.
IC2 is recommended to be an OP-07 or equivalent
device. R2 and R3 must be matched to within 0.1%
with good TC tracking to maintain a 0.3LSB matching
between V_FT and V_FB. If 0.1% matching is not met, then
potentiometer R4 can be used to adjust the V_FB voltage
to the desired level. Adjust R1 and R4 such that V_ST
and V_SB are exactly +2.0V and -2.0V, respectively.
The following errors are defined:
+FS error = top of ladder offset voltage
= ∆(+FS - V_ST)
-FS error = bottom of ladder offset voltage
= ∆(-FS - V_SB)
Where the +FS (full scale) input voltage is defined as
the output 1LSB above the transition of 1–10 and 1–11,
and the -FS input voltage is defined as the output 1LSB
below the transition of 0–00 and 0–01.
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