MAX1171 Datasheet, PDF (10/12 Pages) Maxim Integrated Products – 12-Bit, 20Msps, TTL-Output ADC

12-Bit, 20Msps, TTL-Output ADC
N
CLK IN
2.4V
3.5V
2.4V
DATA OUT
(ACTUAL)
0.8V
0.5V
DATA OUT
(EQUIVALENT)
6ns
typ
(N - 2)
INVALID
DATA
t_PD1
14ns typ
(N - 2)
INVALID
DATA
N+1
(N - 1)
t_RISE
6ns
INVALID
DATA
(N)
(N - 1)
INVALID
DATA
(N - 1)
Figure 4. Digital Output Characteristics
Analog Input
V_IN is the analog input. The full-scale input range will be
80% of the reference voltage or ±2V with V_FB = -2.5V
and V_FT = +2.5V.
The drive requirements for the analog inputs are minimal
compared to those of conventional flash converters, due
to the MAX1171’s extremely low 5pF input capacitance
and high 300kΩ input impedance. For example, for an
input signal of ±2Vp-p with an input frequency of
10MHz, the peak output current required for the driving
circuit is only 628µA.
Clock Input
The MAX1171 is driven from a single-ended TTL input
(CLK). For optimal noise performance, the clock input
slew rate should be a minimum of 6ns. Because of this,
the use of fast logic is recommended. The clock input
duty cycle should be 50% where possible, but perfor-
mance will not be degraded if kept within the range of
40% to 60%. However, in any case, the clock pulse
width (t_PWH) must be kept at 300ns maximum to ensure
proper operation of the internal track/hold amplifier
(Figure 1a). The analog input signal is latched on the
rising edge of the CLK.
The clock input must be driven from fast TTL logic (V_IH ≤
4.5V, t_RISE < 6ns). In the event the clock is driven from a
high current source, use a 100Ω resistor (R1, Figure 2)
in series to current limit to approximately 45mA.
Digital Outputs
The format of the output data (D0-D11) is straight bina-
ry (Table 2). The outputs are latched on the rising edge
of CLK with a typical propagation delay of 14ns. There
is a one clock cycle latency between CLK and the valid
output data (Figure 1a).
The digital outputs’ rise times and fall times are not
symmetrical. The rise time’s typical propagation delay
is 14ns, and the typical fall time is 6ns (Figure 4). The
nonsymmetrical rise and fall times create approximately
8ns of invalid data.
Table 2. Output Data Information
ANALOG
INPUT
> +2.0V + 1/2LSB
+2.0V - 1LSB
0.0V
-2.0V + 1LSB
< -2.0V
OVERRANGE
D10
1
0
0
0
0
OUTPUT CODE
D9–D0
11 1111 1111
11 1111 111Ø
ØØ ØØØØ ØØØØ
00 0000 000Ø
00 0000 0000
(Ø indicates the flickering bit between logic 0 and 1).
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