MAX11202_12 Datasheet, PDF (9/14 Pages) Maxim Integrated Products – 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface

MAX11202
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
Pin Description (continued)
Data Ready Output/Serial Data Output. This output serves a dual function. In addition to the serial
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RDY/DOUT data output function, the RDY/DOUT also indicates that the data is ready when the RDY is logic low.
RDY/DOUT changes on the rising edge of SCLK.
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SCLK Serial Clock Input. Apply an external serial clock to SCLK.
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CLK
External Clock Signal Input. The internal clock shuts down when CLK is driven by an external clock.
Use a 2.4576MHz oscillator (MAX11202A) or a 2.2528MHz oscillator (MAX11202B).
Detailed Description
The MAX11202 is an ultra-low-power (< 240FA active),
high-resolution, low-speed, serial-output ADC. This device
provides the highest resolution per unit power in the
industry and is optimized for applications that require very
high dynamic range with low power such as sensors on a
4mA to 20mA industrial control loop. The MAX11202 pro-
vides a high-accuracy internal oscillator, which requires
no external components. When used with the specified
data rates, the internal digital filter provides more than
80dB rejection of 50Hz or 60Hz line noise. The MAX11202
provides a simple, system-friendly, 2-wire serial interface
in the space-saving, 10-pin FMAX package.
Power-On Reset (POR)
The MAX11202 utilizes power-on reset (POR) supply-
monitoring circuitry on both the digital supply (DVDD)
and the analog supply (AVDD). The POR circuitry
ensures proper device default conditions after either a
digital or analog power-sequencing event.
The MAX11202 performs a self-calibration operation as
part of the startup initialization sequence whenever a
digital POR is triggered. It is important to have a stable
reference voltage available at the REFP and REFN pins
to ensure an accurate calibration cycle. If the reference
voltage is not stable during a POR event, the part should
be calibrated once the reference has stabilized. The part
can be programmed for calibration by using 26 SCLKs
as shown in Figure 3.
The digital POR trigger threshold is approximately 1.2V
and has 100mV of hysteresis. The analog POR trigger
threshold is approximately 1.25V and has 100mV of hys-
teresis. Both POR circuits have lowpass filters that pre-
vent high-frequency supply glitches from triggering the
POR. The analog supply (AVDD) and the digital supply
(DVDD) pins should be bypassed using 0.1µF capaci-
tors placed as close as possible to the package pin.
Analog Inputs
The MAX11202 accepts two analog inputs (AINP and
AINN). The modulator input range is bipolar (-VREF to
+VREF).
Internal Oscillator
The MAX11202 incorporates a highly stable internal
oscillator that provides the system clock. The system
clock runs the internal state machine and is trimmed to
2.4576MHz (MAX11202A) or 2.2528MHz (MAX11202B).
The internal oscillator clock is divided down to run the
digital and analog timing.
Reference
The MAX11202 provides differential inputs REFP and
REFN for an external reference voltage. Connect the
external reference directly across the REFP and REFN
to obtain the differential reference voltage. The common-
mode voltage range for VREFP and VREFN is between 0
and VAVDD. The differential voltage range for REFP and
REFN is 1V to VAVDD.
Digital Filter
The MAX11202 contains an on-chip, digital lowpass filter
that processes the 1-bit data stream from the modulator
using a SINC⁴ (sinx/x)⁴ response. When the device is
operating in single-cycle conversion mode, the filter is
reset at the end of the conversion cycle. When operat-
ing in continuous conversion latent mode, the filter is not
reset. The SINC⁴ filter has a -3dB frequency equal to
24% of the data rate.
Serial-Digital Interface
The MAX11202 communicates through a 2-wire inter-
face, with a clock input and data output. The output
rate is predetermined based on the package option
(MAX11202A at 120sps and MAX11202B at 13.75sps).
Maxim Integrated
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