DS3104 Datasheet, PDF (84/135 Pages) Maxim Integrated Products – Line Card Timing IC with Synchronous Ethernet Support

________________________________________________________________________________________ DS3104-SE
Register Name:
Register Description:
Register Address:
IER3
Interrupt Enable Register 3
45h
Bit #
Name
Default
Bit 7
FSMON
0
Bit 6
T4LOCK
0
Bit 5
—
0
Bit 4
T4NOIN
0
Bit 3
—
0
Bit 2
—
0
Bit 1
—
0
Bit 0
—
0
Bit 7: Interrupt Enable for Frame Sync Input Monitor Alarm (FSMON). This bit is an interrupt enable for the
FSMON bit in the MSR3 register.
0 = Mask the interrupt
1 = Enable the interrupt
Bit 6: Interrupt Enable for the T4 DPLL Lock Status Change (T4LOCK). This bit is an interrupt enable for the
T4LOCK bit in the MSR3 register.
0 = Mask the interrupt
1 = Enable the interrupt
Bit 4: Interrupt Enable for T4 No Valid Inputs Alarm (T4NOIN). This bit is an interrupt enable for the T4NOIN bit
in the MSR3 register.
0 = Mask the interrupt
1 = Enable the interrupt
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