DS3104 Datasheet, PDF (2/135 Pages) Maxim Integrated Products – Line Card Timing IC with Synchronous Ethernet Support

________________________________________________________________________________________ DS3104-SE
Table of Contents
1. STANDARDS COMPLIANCE ..........................................................................................................6
2. APPLICATION EXAMPLE ...............................................................................................................7
3. BLOCK DIAGRAM ...........................................................................................................................8
4. DETAILED DESCRIPTION ..............................................................................................................9
5. DETAILED FEATURES .................................................................................................................11
5.1 INPUT CLOCK FEATURES ...............................................................................................................11
5.2 TIMING CARD TO LINE CARD DPLL FEATURES (T0 DPLL)..............................................................11
5.3 LINE CARD TO TIMING CARD DPLL FEATURES (T4 DPLL)..............................................................11
5.4 OUTPUT APLL FEATURES .............................................................................................................12
5.5 OUTPUT CLOCK FEATURES............................................................................................................12
5.6 GENERAL FEATURES .....................................................................................................................12
6. PIN DESCRIPTIONS ......................................................................................................................13
7. FUNCTIONAL DESCRIPTION .......................................................................................................17
7.1 OVERVIEW ....................................................................................................................................17
7.2 DEVICE IDENTIFICATION AND PROTECTION .....................................................................................18
7.3 LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION.............................................................18
7.4 INPUT CLOCK CONFIGURATION ......................................................................................................19
7.4.1 Signal Format Configuration ................................................................................................................ 19
7.4.2 Frequency Configuration...................................................................................................................... 20
7.5 INPUT CLOCK MONITORING............................................................................................................21
7.5.1 Frequency Monitoring .......................................................................................................................... 21
7.5.2 Activity Monitoring ................................................................................................................................ 21
7.5.3 Selected Reference Activity Monitoring ............................................................................................... 21
7.6 INPUT CLOCK PRIORITY, SELECTION AND SWITCHING.....................................................................22
7.6.1 Priority Configuration............................................................................................................................ 22
7.6.2 Automatic Selection Algorithm ............................................................................................................. 22
7.6.3 Forced Selection .................................................................................................................................. 23
7.6.4 Ultra-Fast Reference Switching ........................................................................................................... 23
7.6.5 External Reference Switching Mode.................................................................................................... 24
7.6.6 Output Clock Phase Continuity During Reference Switching .............................................................. 24
7.7 DPLL ARCHITECTURE AND CONFIGURATION ..................................................................................25
7.7.1 T0 DPLL State Machine ....................................................................................................................... 26
7.7.2 T4 DPLL State Machine ....................................................................................................................... 29
7.7.3 Bandwidth ............................................................................................................................................ 31
7.7.4 Damping Factor.................................................................................................................................... 31
7.7.5 Phase Detectors................................................................................................................................... 31
7.7.6 Loss of Phase Lock Detection ............................................................................................................. 32
7.7.7 Phase Build-Out ................................................................................................................................... 33
7.7.8 Input to Output (Manual) Phase Adjustment........................................................................................ 33
7.7.9 Phase Recalibration ............................................................................................................................. 33
7.7.10 Frequency and Phase Measurement................................................................................................... 34
7.7.11 Input Jitter Tolerance ........................................................................................................................... 35
7.7.12 Jitter and Wander Transfer .................................................................................................................. 35
7.7.13 Output Jitter and Wander ..................................................................................................................... 36
7.8 OUTPUT CLOCK CONFIGURATION...................................................................................................37
7.8.1 Signal Format Configuration ................................................................................................................ 37
7.8.2 Frequency Configuration...................................................................................................................... 37
7.9 FRAME AND MULTIFRAME ALIGNMENT ............................................................................................45
7.9.1 Sampling .............................................................................................................................................. 45
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