MAX1624 Datasheet, PDF (8/24 Pages) Maxim Integrated Products – High-Speed Step-Down Controllers with Synchronous Rectification for CPU Power

High-Speed Step-Down Controllers with
Synchronous Rectification for CPU Power
______________________________________________________________Pin Description
PIN
MAX1624 MAX1625
1
1
2
2
3
3
4
4
5, 6, 7
—
8
—
9
5
10
6
11
7
12
8
13
9
14
10
15
11
16, 17
—
18
—
19
—
20
12
21
13
22
14
23
15
24
16
NAME
BST
PWROK
CSL
CSH
D2, D1,
D0
LG
V_CC
REF
AGND
FB
CC1
CC2
FREQ
D4, D3
NDRV
PDRV
V_DD
DL
PGND
LX
DH
FUNCTION
Boost-Capacitor Bypass for High-Side MOSFET Gate Drive. Connect a 0.1µF capacitor
and low-leakage Schottky diode as a bootstrapped charge-pump circuit to derive a 5V
gate drive from V_DD for DH.
Open-Drain Logic Output. PWROK is high when the voltage on FB is within +8% and -6%
of its setpoint.
Current-Sense Amplifier’s Inverting Input. Place the current-sense resistor very close to
the controller IC, and use a Kelvin connection. Use an RC filter network at CSL (Figure 1).
Current-Sense Amplifier’s Noninverting Input. Use an RC filter network at CSH (Figure 1).
Digital Inputs for Programming the Output Voltage. D0–D4 are logic inputs that set the
output to a voltage between 1.1V and 3.5V in 100mV increments.
Loop Gain-Control Input. LG is a three-level input that is used to trade off loop gain vs.
AC load-regulation and load-transient response. Connect LG to V_CC, REF, or AGND for
2%, 1%, or 0.5% AC load-regulation errors, respectively.
Analog Supply Input, 5V. Use an RC filter network, as shown in Figure 1.
Reference Output, 3.5V. Bypass REF to AGND with 0.1µF (min). Sources up to 100µA for
external loads. Force REF below 2V to turn off the controller.
Analog Ground
Voltage-Feedback Input.
MAX1624: Connect FB to the CPU’s remote voltage-sense point. The voltage at this
input is regulated to a value determined by D0–D4.
MAX1625: Connect a feedback resistor voltage divider close to FB from the output to
AGND. FB is regulated to 1.1V.
Fast-Loop Compensation Capacitor Input. Connect a ceramic capacitor and resistor in
series from CC1 to AGND. See the section Compensating the Feedback Loop.
Slow-Loop Compensation Capacitor Input. Connect a ceramic capacitor from CC2 to
AGND. See the section Compensating the Feedback Loop.
Frequency-Programming Input. Attach a resistor within 0.2 in. (5mm) of FREQ to AGND to
set the switching frequency between 100kHz and 1MHz. The FREQ pin is normally 2V DC.
Digital Inputs for Programming the Output Voltage
GlitchCatcher N-Channel MOSFET Driver Output. NDRV swings between V_DD and
PGND.
GlitchCatcher P-Channel MOSFET Driver Output. PDRV swings between V_DD and PGND.
5V Power Input for MOSFET Drivers. Bypass V_DD to PGND within 0.2 in. (5mm) of the
V_DD pin using a 0.1µF capacitor and 4.7µF capacitor connected in parallel.
Low-Side Synchronous Rectifier Gate-Drive Output. DL swings between PGND and V_DD.
See the section BST High-Side Gate-Driver Supply and MOSFET Drivers.
Power Ground
Switching Node. Connect LX to the high-side MOSFET source and inductor.
High-Side Main MOSFET Switch Gate-Drive Output. DH is a floating driver output that
swings from LX to BST, riding on the LX switching-node voltage. See the section BST
High-Side Gate-Driver Supply and MOSFET Drivers.
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