MAX1624 Datasheet, PDF (19/24 Pages) Maxim Integrated Products – High-Speed Step-Down Controllers with Synchronous Rectification for CPU Power

High-Speed Step-Down Controllers with
Synchronous Rectification for CPU Power
Compensating the Feedback Loop
The feedback loop needs proper compensation to pre-
vent excessive output ripple and poor efficiency
caused by instability. Compensation cancels unwanted
poles and zeros in the DC-DC converter’s transfer func-
tion that are due to the power-switching and filter ele-
ments with corresponding zeros and poles in the
feedback network. These compensation zeros and
poles are set by the compensation components CC1,
CC2, and RC1. The objective of compensation is to
ensure stability by ensuring that the DC-DC converter’s
phase shift is less than 180° by a safe margin, at the
frequency where the loop gain falls below unity.
One simple method for ensuring adequate phase mar-
gin is to place pole-zero pairs to approximate a single-
pole response with a -20dB/decade slope all the way to
unity-gain crossover (Figure 8). (Other compensation
schemes are possible.) The order of undesired poles
and zeros may differ from that shown in Figure 8,
depending on the characteristics of the load, output
filter capacitor, switching frequency, and inductor.
These procedures are guidelines only, and empirical
experimentation is needed to select the compensation
components’ final values.
LOOP
GAIN
DOMINANT POLE
1
FROM INTEGRATOR 2π50kΩ x CC2
COMPENSATION ZERO
TO CANCEL POLE FROM
R_LOAD C_OUT 1mmho
2π x 4CC2
UNWANTED
1
POLE FROM
R_LOAD C_OUT
2πR_LOAD(MAX) x C_OUT
UNWANTED ZERO
1
FROM C_OUT R_ESR 2πRESR x COUT
COMPENSATION
1
POLE TO CANCEL _{2π(10kΩ x CC1)}
ZERO FROM
C_OUT R_ESR
COMPENSATION
ZERO TO CANCEL
SAMPLING POLE
UNWANTED
SAMPLING POLE
DESIRED
1
RESPONSE
f_OSC(MIN)
(1 + D_MAX) x π
2π(RC1 x CC1)
FREQUENCY (LOG)
Canceling the Sampling Pole
and Output Filter ESR Zero
Compensate the fast-voltage feedback loop by con-
necting a resistor and a capacitor in series from the
CC1 pin to AGND. The pole from CC1 can be set to
cancel the zero from the filter-capacitor ESR. Thus the
capacitor at CC1 should be as follows:
CC1 = ^{COUT x RESR}
10kΩ
Resistor RC1 sets a zero that can be used to compen-
sate for the sampling pole generated by the switching
frequency. Set RC1 to the following:
RC1 =
_{1 +}
V_OUT 
V_IN 
2f_OSC x CC1
The CC1 pin’s output resistance is 10kΩ. In the sam-
pling pole equation (Figure 8), D_MAX is the maximum
duty cycle, or V_OUT / V_IN(MIN).
Setting the Dominant Pole
and Canceling the Load and Output Filter Pole
Compensate the slow-voltage feedback loop by adding
a ceramic capacitor from the CC2 pin to AGND. This is
an integrator loop used to cancel out the DC load-
regulation error. Selection of capacitor CC2 sets the
dominant pole and a compensation zero. The zero is
typically used to cancel the unwanted pole generated
by the load and output filter capacitor at the maximum
load current. Select CC2 to place the zero close to or
slightly lower than the frequency of the unwanted pole,
as follows:
CC2 = ^{1mmho x COUT} x ^VOUT
4
I_OUT(MAX)
The transconductance of the integrator amplifier at CC2
is 1mmho. The voltage swing at CC2 is internally
clamped around 2.4V to 3V minimum and 4V to V_CC
maximum to improve transient response times. CC2
can source and sink up to 100µA.
Figure 8. MAX1624/MAX1625 Bode Plot with Compensation
Poles and Zeros
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