MAX1473_12 Datasheet, PDF (8/16 Pages) Maxim Integrated Products – 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range

315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Pin Description
PIN
TSSOP TQFN
1
29
2, 7 4, 30
3
31
4
32
5
2
6
3
8
5
9
6
10
7
11
8
12
9
13
10
14
11
15
12
16
14
17
15
18
16
19
17
20
18
21
19
22
20
23
22
24
23
25
24
26
26
27
27
28
28
—
1, 13,
21, 25
—
—
NAME
FUNCTION
XTAL1 1st Crystal Input. (See the Phase-Locked Loop section.)
AVDD
Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.2V
low-dropout regulator and should be bypassed to AGND with a 0.1µF capacitor as close as
possible to the pin. Pin 7 must be externally connected to the supply from pin 2 and bypassed to
AGND with a 0.01µF capacitor as close as possible to the pin (see the Voltage Regulator section
and the Typical Application Circuit).
LNAIN Low-Noise Amplifier Input. (See the Low-Noise Amplifier section.)
LNASRC
AGND
Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground to set
LNA input impedance. (See the Low-Noise Amplifier section.)
Analog Ground
LNAOUT
MIXIN1
Low-Noise Amplifier Output. Connect to mixer through an LC tank filter. (See the Low-Noise
Amplifier section.)
1st Differential Mixer Input. Connect through a 100pF capacitor to V_DD3 side of the LC tank.
MIXIN2 2nd Differential Mixer Input. Connect through a 100pF capacitor to LC tank filter from LNAOUT.
AGND Analog Ground
IRSEL
MIXOUT
Image Rejection Select Pin. Set V_IRSEL = 0V to center image rejection at 315MHz. Leave IRSEL
unconnected to center image rejection at 375MHz. Set V_IRSEL = V_DD to center image rejection at 433MHz.
330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
DGND Digital Ground
DVDD
Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a 0.01µF
capacitor as close as possible to the pin (see the Typical Application Circuit).
AGCDIS AGC Control Pin. Pull high to disable AGC.
XTALSEL
IFIN1
IFIN2
Crystal Divider Ratio Select Pin. Drive XTALSEL low to select divider ratio of 64, or drive XTALSEL
high to select divider ratio of 32.
1st Differential Intermediate Frequency Limiter Amplifier Input. Decouple to AGND with a 1500pF
capacitor.
2nd Differential Intermediate Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz
bandpass filter.
DFO Data Filter Output
DSN Negative Data Slicer Input
OPP Noninverting Op-Amp Input for the Sallen-Key Data Filter
DFFB Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
DSP Positive Data Slicer Input
V_DD5
+5V Supply Voltage. Bypass to AGND with a 0.01µF capacitor as close as possible to the pin. For
+5V operation, V_DD5 is the input to an on-chip voltage regulator whose +3.2V output appears at the
pin 2 AVDD pin. (See the Voltage Regulator section and the Typical Application Circuit.)
DATAOUT Digital Baseband Data Output
PDOUT Peak Detector Output
PWRDN Power-Down Select Input. Drive this pin with a logic high to power on the IC.
XTAL2 2nd Crystal Input
N.C. No Connection
EP
Exposed Pad (TQFN Only). Connect EP to GND.
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