MAX1391 Datasheet, PDF (8/18 Pages) Maxim Integrated Products – 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/2-Channel Single-Ended, 8-Bit, SAR ADCs

1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
Pin Description
PIN
MAX1391 MAX1394
1
1
2
—
—
2
3
—
—
3
4
4
5
5
6
—
—
6
7
7
8
8
9
9
10
10
—
—
NAME
V_DD
AIN-
AIN2
AIN+
AIN1
GND
REF
UNI/BIP
CH1/CH2
OE
CS
DOUT
SCLK
EP
FUNCTION
Positive Supply Voltage. Connect V_DD to a 1.6V to 3.6V power supply. Bypass V_DD to GND
with a 0.1µF capacitor as close as possible to the device.
Negative Analog Input
Analog Input Channel 2
Positive Analog Input
Analog Input Channel 1
Ground
External Reference Voltage Input. V_REF = 0.6V to (V_DD + 0.05V). Bypass REF to GND with a
0.1µF capacitor as close as possible to the device.
Input-Mode Select. Drive UNI/BIP high to select unipolar input mode. Pull UNI/BIP low to
select bipolar input mode. In unipolar mode, the output data is in straight binary format. In
bipolar mode, the output data is in two’s complement format.
Channel-Select Input. Pull CH1/CH2 low to select channel 1. Drive CH1/CH2 high to select
channel 2.
Active-Low Output Enable. Pull OE low to enable DOUT. Drive OE high to disable DOUT.
Connect to CS to interface with SPI, QSPI, and MICROWIRE devices or set low to interface
with DSP devices.
Active-Low Chip-Select Input. A falling edge on CS initiates power-up and acquisition.
Serial-Data Output. DOUT changes state on the falling edge of SCLK. DOUT is high
impedance when OE is high.
Serial-Clock Input. SCLK drives the conversion process and clocks data out. Acquisition ends
on the 3rd falling edge after the CS falling edge. The LSB is clocked out on the SCLK 11th
falling edge and the device enters AutoShutdown mode (see Figures 8, 9, and 10).
Exposed Pad. Not internally connected. Connect the exposed pad to GND or leave floating.
Detailed Description
The MAX1391/MAX1394 use an input track and hold
(T/H) circuit along with a SAR to convert an analog input
signal to a serial 8-bit digital output data stream. The seri-
al interface provides easy interfacing to microprocessors
and DSPs. Figure 3 shows the simplified functional dia-
gram for the MAX1391 (1 channel, true differential) and
the MAX1394 (2 channels, single ended).
True-Differential Analog Input T/H
The equivalent input circuit of Figure 4 shows the
MAX1391/MAX1394 input architecture that is composed
of a T/H, a comparator, and a switched-capacitor DAC.
The T/H enters its tracking mode on the falling edge of
CS (while OE is held low). The positive input capacitor is
connected to AIN+ (MAX1391), or to AIN1 or AIN2
(MAX1394). The negative input capacitor is connected to
AIN- (MAX1391) or GND (MAX1394). The T/H enters its
hold mode on the 3rd falling edge of SCLK and the dif-
V_DD
CONTROL
LOGIC AND
TIMING
AIN+ (AIN1)*
AIN- (AIN2)*
REF
INPUT
MUX
AND T/H
8-BIT SAR
ADC
OUTPUT
SHIFT
REGISTER
MAX1391
MAX1394
GND
*INDICATES THE MAX1394
Figure 3. Simplified Functional Diagram
8 _______________________________________________________________________________________
CS
SCLK
OE
DOUT
UNI/BIP
(CH1/CH2)*