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MAX1391 Datasheet, PDF (4/18 Pages) Maxim Integrated Products – 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/2-Channel Single-Ended, 8-Bit, SAR ADCs
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1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Positive Supply Current (Note 4)
fSAMPLE = 100ksps
VDD = 1.6V
VDD = 3V
IDD
fSAMPLE = 416ksps
VDD = 1.6V
VDD = 3V
Power-down mode (Note 5)
125
150
150
200
520
600
µA
710
800
5
10
Power-down mode (Note 6)
0.2 ±2.5
Power-Supply Rejection
PSR VDD = 1.6V to 3.6V, full-scale input (Note 7)
±150 ±1000 µV/V
TIMING CHARACTERISTICS
(VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.) (Figure 1)
PARAMETER
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Fall to SCLK Rise Setup
SCLK Rise to CS Fall Ignore
SCLK Fall to DOUT Valid
OE Rise to DOUT Disable
OE Fall to DOUT Enable
CS Pulse-Width High and Low
OE Pulse-Width High and Low
CH1/CH2 Setup Time (to the First
SCLK)
CH1/CH2 Hold Time (to the First
SCLK)
UNI/BIP Setup Time (to the First
SCLK)
UNI/BIP Hold Time (to the First
SCLK)
SYMBOL
tCP
tCH
tCL
tCSS
tCSO
tDOV
tDOD
tDOE
tCSW
tOEW
CONDITIONS
CLOAD = 0 to 30pF
tCHS MAX1394 only
tCHH MAX1394 only
tUBS MAX1391 only
tUBH MAX1391 only
MIN TYP MAX UNITS
200
10,000 ns
90
ns
90
ns
80
ns
0
ns
10
80
ns
6
20
ns
9
20
ns
80
ns
80
ns
10
ns
0
ns
10
ns
0
ns
Note 1: Devices are production tested at room and +85°C. Specification to -40°C are guaranteed by design.
Note 2: VDD = 1.6V, VREF = 1.6V, and VAIN = 1.6V.
Note 3: VDD = 1.6V, VREF = 1.6V, VAIN = 1.6VP-P, fSCLK = 5MHz, fSAMPLE = 416ksps, and fIN (sine wave) = 100kHz.
Note 4: All digital inputs swing between VDD and GND. VREF = VDD, fIN = 100kHz sine wave, VAIN = VREFP-P, CLOAD = 30pF on DOUT.
Note 5: CS = VDD, OE = UNI/BIP = CH1/CH2 = VDD or GND, SCLK is active.
Note 6: CS = VDD, OE = UNI/BIP = CH1/CH2 = VDD or GND, SCLK is inactive.
Note 7: Change in VAIN at code boundary 254.5.
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