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MAX13035EETE Datasheet, PDF (8/18 Pages) Maxim Integrated Products – 6-Channel High-Speed Logic-Level Translators
6-Channel High-Speed Logic-Level Translators
Pin Description
PIN
MAX13030E–MAX13034E
UCSP
TQFN
A1
4
A2
6
A3
7
A4
9
B1
3
B2
5
B3
8
B4
10
MAX13035E
UCSP TQFN
A1
4
A2
6
A3
7
A4
9
B1
3
B2
5
B3
8
B4
10
C1
2
C1
2
C2
16
C2
16
C3
13
C3
13
C4
11
—
—
D1
1
D1
1
D2
15
D2
15
D3
14
—
—
D4
12
—
—
—
—
C4
11
—
—
D3
14
—
—
D4
12
—
EP
—
EP
NAME
FUNCTION
I/O VL3
I/O VCC3
I/O VCC4
I/O VL4
I/O VL2
I/O VCC2
I/O VCC5
I/O VL5
VL
Input/Output 3. Referenced to VL.
Input/Output 3. Referenced to VCC.
Input/Output 4. Referenced to VCC.
Input/Output 4. Referenced to VL.
Input/Output 2. Referenced to VL.
Input/Output 2. Referenced to VCC.
Input/Output 5. Referenced to VCC.
Input/Output 5. Referenced to VL.
Logic-Supply Voltage, +1.62V to +3.2V. Bypass VL to GND with
a 0.1µF capacitor placed as close as possible to the device.
Power-Supply Voltage, +2.2V to +3.6V. Bypass VCC to GND with
VCC
a 0.1µF ceramic capacitor. For full ESD protection, connect a
1µF ceramic capacitor from VCC to GND as close as possible to
the VCC input.
GND Ground
EN
I/O VL1
I/O VCC1
I/O VCC6
I/O VL6
CLK_RET
CLK_VCC
CLK_VL
EP
Enable Input. Drive EN to GND for shutdown mode, or drive EN to
VL or VCC for normal operation.
Input/Output 1. Referenced to VL.
Input/Output 1. Referenced to VCC.
Input/Output 6. Referenced to VCC.
Input/Output 6. Referenced to VL.
Clock Return Output. CLK_RET is the returned signal of a clock
applied to CLK_VL. CLK_RET is referenced to VL.
Translator Channel for a Clock Applied to VCC
Translator Channel for a Clock Applied to VL
Exposed Paddle. Connect exposed paddle to GND.
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