MAX1240_10 Datasheet, PDF (8/15 Pages) Maxim Integrated Products – +2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO

+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
+2.7V to +3.6V*
4.7μF 0.1μF _{1 VDD}
* V_DD,MAX = +5.25V (MAX1241)
** 4.7μF (MAX1240)
0.1μF (MAX1241)
SCLK ⁸
ANALOG INPUT
0V TO V_REF
SHUTDOWN
INPUT
REFERENCE
INPUT
(MAX1241 ONLY)
2 _{AIN MAX1240 CS} 7
MAX1241
3
SHDN
6
DOUT
4 _REF
GND ⁵
C**
SERIAL
INTERFACE
12-BIT CAPACITIVE DAC
REF
AIN
TRACK _INPUT ^CHOLD
COMPARATOR
ZERO
-+
HOLD
16pF
9k
C_SWITCH
R_IN
HOLD
TRACK
AT THE SAMPLING INSTANT,
THE INPUT SWITCHES FROM
AIN TO GND.
GND
Figure 3. Operational Diagram
Figure 4. Equivalent Input Circuit
_______________Detailed Description
Converter Operation
The MAX1240/MAX1241 use an input track/hold (T/H)
and successive-approximation register (SAR) circuitry
to convert an analog input signal to a digital 12-bit out-
put. No external-hold capacitor is needed for the T/H.
Figure 3 shows the MAX1240/MAX1241 in its simplest
configuration. The MAX1240/MAX1241 convert input
signals in the 0V to V_REF range in 9µs, including T/H
acquisition time. The MAX1240’s internal reference is
trimmed to 2.5V, while the MAX1241 requires an external
reference. Both devices accept voltages from 1.0V to
V_DD. The serial interface requires only three digital lines
(SCLK, CS, and DOUT) and provides an easy interface
to microprocessors (µPs).
The MAX1240/MAX1241 have two modes: normal and
shutdown. Pulling SHDN low shuts the device down and
reduces supply current below 10µA (V_DD ≤ 3.6V), while
pulling SHDN high or leaving it open puts the device
into operational mode. Pulling CS low initiates a conver-
sion. The conversion result is available at DOUT in
unipolar serial format. The serial data stream consists
of a high bit, signaling the end of conversion (EOC), fol-
lowed by the data bits (MSB first).
Analog Input
Figure 4 illustrates the sampling architecture of the ana-
log-to-digital converter’s (ADC’s) comparator. The full-
scale input voltage is set by the voltage at REF.
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input (AIN) charges
capacitor C_HOLD. Bringing CS low ends the acquisition
interval. At this instant, the T/H switches the input side
of C_HOLD to GND. The retained charge on C_HOLD repre-
sents a sample of the input, unbalancing node ZERO at
the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0V within the limits of 12-
bit resolution. This action is equivalent to transferring a
charge from C_HOLD to the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
side of C_HOLD switches back to AIN, and C_HOLD
charges to the input signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(t_ACQ) is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. Acquisition time is calculated by:
t_ACQ = 9(R_S + R_IN) x 16pF
where R_IN = 9kΩ, R_S = the input signal’s source imped-
ance, and t_ACQ is never less than 1.5µs. Source imped-
ances below 1kΩ do not significantly affect the ADC’s
AC performance.
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