MAX1240_10 Datasheet, PDF (10/15 Pages) Maxim Integrated Products – +2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO

+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
ed. After an internally timed conversion period, the end
of conversion is signaled by DOUT pulling high. Data
can then be shifted out serially with the external clock.
Using SHDN to Reduce Supply Current
Power consumption can be reduced significantly by
shutting down the MAX1240/MAX1241 between con-
versions. Figure 6 shows a plot of average supply cur-
rent versus conversion rate. Because the MAX1241
uses an external reference voltage (assumed to be pre-
sent continuously), it “wakes up” from shutdown more
quickly (in 4µs) and therefore provides lower average
supply currents. The wake-up time (t_WAKE) is the time
from when SHDN is deasserted to the time when a con-
version may be initiated (Figure 5). For the MAX1240,
this time depends on the time in shutdown (Figure 7)
because the external 4.7µF reference bypass capacitor
loses charge slowly during shutdown.
External Clock
The actual conversion does not require the external
clock. This allows the conversion result to be read back
at the µP’s convenience at any clock rate from up to
2.1MHz. The clock duty cycle is unrestricted if each
clock phase is at least 200ns. Do not run the clock
while a conversion is in progress.
Timing and Control
Conversion-start and data-read operations are controlled
by the CS and SCLK digital inputs. The timing diagrams
of Figures 8 and 9 outline serial-interface operation.
A CS falling edge initiates a conversion sequence: the
T/H stage holds the input voltage, the ADC begins to
convert, and DOUT changes from high impedance to
logic low. SCLK must be kept low during the conver-
sion. An internal register stores the data when the con-
version is in progress.
10
V_DD = V_REF = 3.0V
R_LOAD = ∞, C_LOAD = 50pF
CODE = 010101010000
1
0.1
MAX1240
0.01
MAX1241
0.001
0.1
1 10 100 1k 10k 100k
CONVERSION RATE (Hz)
Figure 6. Average Supply Current vs. Conversion Rate
1.0
0.8
0.6
0.4
0.2
0.0
0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (sec)
Figure 7. Typical Reference Power-Up Delay vs. Time in
Shutdown
CS
SCLK
DOUT
INTERFACE IDLE
TRACK/HOLD
STATE TRACK
CYCLE TIME
CONVERSION
IN PROGRESS
HOLD
7.5μs (t_CONV)
1
4
8
12
16
EOC
EOC
0μs
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CLOCK OUT SERIAL DATA
TRACK
12.5 × 0.476μs = 5.95μs
TOTAL = 13.7μs
TRAILING
ZEROS
0μs
IDLE
0.24μs
(t_CS)
HOLD
Figure 8. Interface Timing Sequence
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