MAX1165-MAX1166 Datasheet, PDF (8/15 Pages) Maxim Integrated Products – Low-Power, 16-Bit Analog-to-Digital Converters with Parallel Interface

Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
DV_DD
1mA
D0–D15
1mA
DGND
C_LOAD = 20pF
D0–D15
C_LOAD = 20pF
DGND
a) HIGH-Z TO V_OH, V_OL TO V_OH,
AND V_OH TO HIGH-Z
b) HIGH-Z TO V_OL, V_OH TO V_OL,
AND V_OL TO HIGH-Z
Figure 1. Load Circuits
Detailed Description
Converter Operation
The MAX1165/MAX1166 use a successive-approxima-
tion (SAR) conversion technique with an inherent track-
and-hold (T/H) stage to convert an analog input into a
16-bit digital output. Parallel outputs provide a high-
speed interface to most microprocessors (µPs). The
Functional Diagram shows a simplified internal archi-
tecture of the MAX1165/MAX1166. Figure 3 shows a
typical application circuit for the MAX1166.
Analog Input
The equivalent input circuit is shown in Figure 4. A
switched capacitor digital-to-analog converter (DAC)
provides an inherent T/H function. The single-ended
input is connected between AIN and AGND.
Input Bandwidth
The ADC’s input-tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use anti-alias filtering.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to AV_DD and/or AGND, allow the input to swing
from AGND - 0.3V to AV_DD + 0.3V, without damaging
the device.
If the analog input exceeds 300mV beyond the sup-
plies, limit the input current to 10mA.
CS
R/C
EOC
D0–D15
t_CSL
t_CSH
t_ACQ
REF POWER-
DOWN BIT
t_DH
t_DS
HIGH-Z
t_CONV
t_DV
t_DO
t_EOC
DATA VALID
t_BR
HIGH-Z
HBEN*
D8/D15–
D0/D7*
*HBEN AND BYTE-WIDE DATA BUS
AVAILABLE ON MAX1166 ONLY.
t_DO1
HIGH-/LOW-
BYTE VALID
t_BR
HIGH-/LOW-
BYTE VALID
Figure 2. MAX1165/MAX1166 Timing Diagram
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